High-Voltage Linear Regulator; Voltage Regulator Enable And Reset; Power Sequencing - Laird BT800 Series Hardware Integration Manual

BT800-ST Hardware Integration Guide
Version 1.5

9.2 High-voltage Linear Regulator

The integrated high-voltage linear regulator is available to power the main 1.8 V supply rail. The input voltage range
is between 2.3 V and 4.8 V. The maximum current from this regulator is 100 mA. Internally decouple the output of
this regulator using a low ESR MLC capacitor of a 2.2 µF to the VREG_OUT_HV pin. No externally decouple capacitor
is required. For hassle environment, an output capacitor of 1 µF to 4.7 µF (±20%) is preferred. Take VREG_EN_RST#
high to enable this regulator. If this regulator is not required, then leave VREG_IN_HV unconnected or tied to
VREG_OUT_HV.

9.3 Voltage Regulator Enable and Reset

A single pin, VREG_EN_RST#, controls both the regulator enables and the digital reset function. All the regulators
are enabled, except the USB linear regulator, by taking the VREG_EN_RST# pin above 1 volt. Software also controls
the regulators. The VREG_EN_RST# pin is connected internally to the reset function and is powered from
VDD_HOST, so do not apply voltages above VDD_HOST to the VREG_EN_RST# pin. The REG_EN_RST# pin is pulled
down internally before the software starts. The VREG_EN_RST# pin is an active low reset. Assert the reset signal for
a period >5 ms to ensure a full reset.
Note: The regulator enables are released as soon as VREG_EN_RST# is low, so the regulators shut down.
Therefore do not take VREG_EN_RST# low for less than 5 ms, as a full reset is not guaranteed.
Other reset sources are:
Power-on reset
Via a software-configured watchdog timer
A warm reset function is also available under software control. After a warm reset the RAM data remains
available.

9.4 Power Sequencing

CSR recommends that all power supplies are powered at the same time. The order of powering the supplies relative
to the I/O supply, VDD_PADS to VDD_HOST, is not important. If the I/O supply is powered before VDD_DIG, all
digital I/Os are weak pull-downs regardless of the reset state.
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