Pcm_Clk And Pcm_Sync Generation - Laird BT800 Series Hardware Integration Manual

BT800-ST Hardware Integration Guide
Version 1.5
Figure 12: PCM Slave Timing Short Frame Sync

8.10 PCM_CLK and PCM_SYNC Generation

BT800 has two methods of generating PCM_CLK and PCM_SYNC in master mode:
Generating these signals by DDS from BT800internal 4MHz clock. Using this mode limits PCM_CLK to 128,

256 or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of frequencies

to be generated with low jitter but consumes more power. To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
Equation 8.1 describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 8.1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using
Equation 8.2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set SKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
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Equation 8.2:
19 Laird