DFI 686IPK User Manual page 49

Auto Configuration
DRAM RAS# Precharge Time
MA Additional Wait State
RAS# To CAS# Delay
DRAM Read Burst (B/E/F)
DRAM Write Burst (B/E/F)
ISA Bus Clock
DRAM Fast Leadoff
DRAM Refresh Queue
DRAM RAS Only Refresh
DRAM ECC/Parity Select
Fast DRAM Refresh
Read-Around-Write
PCI Burst Write Combine
PCI-To-DRAM Pipeline
CPU-To-PCI Write Post
CPU-To-PCI IDE Posting
Auto Configuration
Enabled The system will set the " DRAM RAS# Precharge Time" to
the " ISA Bus Clock" categories automatically.
Disabled This allows you to set the " DRAM RAS# Precharge Time" to
the " ISA Bus Clock" categories manually.
DRAM ECC/Parity Select
Parity Enables the memory parity check. If the system DRAM has no
parity bit, the system will display " RAM parity error" .
Disabled The system will ignore the memory parity check even if the
DRAM has no parity bit. The system will not display " RAM
parity error" .
ECC Enables the ECC (Error Correction Code) function.
ISA Bus Clock
PCICLK/4 The PCI Bus Clock is 33MHz and the ISA bus clock is
8.25MHz.
PCICLK/3 The PCI Bus Clock is 33MHz and the ISA bus clock is
11MHz.
Warning:
We recommend that you set the ISA Bus Clock category to " PCICLK/4" . Compatibility
problems with some ISA cards may occur if the ISA Bus Clock is set at " PCICLK/3" .
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: Enabled System BIOS Cacheable
Video BIOS Cacheable
: 4 VGA Write Combining
: Disabled 8 Bit I/O Recovery Time
: Enabled 16 Bit I/O Recovery Time
: x2/3/4 Memory Hole At 15M-16M
: x3/3/3
Passive Release
: PCICLK/4 Delayed Transaction
: Disabled
: Enabled
: Disabled
: Disabled
: Disabled
↑ ↓ → ←
ESC : Quit
: Enabled
F1 : Help PU/PD/+/-
: Disabled
: Enabled F5 : Old Values (Shift) F2
: Enabled
F6 : Load BIOS Defaults
: Disabled
F7 : Load Setup Defaults
: Disabled
: Enabled
: Disabled
: 4
: 2
: Disabled
: Enabled
: Disabled
: Select Item
: Modify
: Color
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