Advantech ARK-3531 Series User Manual page 65

PEG Link and Speed Information
Enable Root Port

Enable or Disable the Root Port.
Max Link Speed

Configure PEG Max Speed.
PEG0 Slot Power Limit Value

Sets the upper limit on power supplied by slot. Power limit (in Watts) is calcu-
lated by multiplying this value by the Slot Power Limit Scale. Values 0-255.
PEG0 Slot Power Limit Scale

Select the scale used for the Slot Power Limit Value.
PEG0 Physical Slot Number

Set the physical slot number attached to this Port. The number has to be glob-
ally unique within the chassis. Values 0-8191.
Detect Non-Compliance Device

Detect Non-Compliance PCI Express Device in PEG.
Program PCIe ASPM after OpROM

Enabled: PCIe ASPM will be programmed after OpROM.\nDisabled: PCIe
ASPM will be programmed before OpROM.
PCIe Spread Spectrum Clocking

Allows disabling Spread Spectrum Clocking for compliance testing.
VT-d

VT-d capability.
Above 4GB MMIO BIOS assignment

Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\n. This is
enabled automatically when Aperture Size is set to 2048MB.
Program PCIe ASPM after OpROM

Enable PCI Express Active State Power Management settings.
PCIe Spread Spectrum Clocking

Enable or Disable PCIe Spread Spectrum Clocking.
53 ARK-3531 User Manual