Lclk Clock Gating In L1 - Silicon Graphics Rackable H2106-G7 System User's Manual

Powerdown Unused Lanes
Turnoff Off PLL During L1/L23
TX Drive Strength
TXCLK Clock Gating in L1

LCLK Clock Gating in L1

SB Core Settings
TX Drive Strength
TXCLK Clock Gating in L1
LCLK Clock Gating in L1
007-5683-004
This setting allows you to Enable or Disable the powerdown of unused lanes.
This setting allows you to Enable or Disable turning off PLL during L1/L23.
Use this setting to configure TX drive strength. Options include Auto, 26mA, 20mA, 22mA and
24mA.
Use this setting to Enable or Disable the TXCLK clock gating in L1.
Use this setting to Enable or Disable the LCLK clock gating in L1.
Use this setting to configure TX drive strength. Options include Auto, 26mA, 20mA, 22mA and
24mA.
Use this setting to Enable or Disable the TXCLK clock gating in L1.
Use this setting to Enable or Disable the LCLK clock gating in L1.
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