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2
General Configuration and Description
2.1
Physical Access
Table 2
lists the TPS2480/1EVM connector functionality, and
Connector
Label
J1/J6
+IN/–IN
J3/J8
+IN/–IN
J2/J5
+OUT/–OUT
J4/J7
+OUT/–OUT
J13
USB
J9
A1
J10
A0
S1
EN
J11, J12
Test Point
Color
TP2
RED
TP5
BLK
TP3
ORG
TP4
BLK
TP1
WHT
TP6
WHT
TP10
WHT
TP16
WHT
TP18
WHT
TP15
WHT
TP14
WHT
TP13
WHT
TP12
WHT
TP11
WHT
TP17
RED
TP19
BLK
TP7
WHT
TP9
WHT
TP8
RED
D6
GRN
SLUU370A – January 2010 – Revised June 2010
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Table 2. Connector Functionality
Description
Power bus input (high-current, screw-down lugs). J1 is +IN and J6 is –IN. Apply bus input voltage
between either J1/J6 or between J3/J8.
Power bus input (banana jack). J3 is +IN and J8 is –IN. Apply bus input voltage between either J1/J6
or between J3/J8.
Switched bus output (high-current, screw-down lugs). J2 is +OUT and J5 is –OUT. Apply the load
between either J2/J5 or between J4/J7.
Switched bus output (banana jack). J4 is +OUT and J7 is –OUT. Apply the load between either J2/J5
or between J4/J7.
USB port. Connect furnished USB cable to PC when using the TPS2480/1 GUI
Allows selection of the A1 I2C address bit. The EVM default is set to address 1000000 by R13/R14.
For other address options, remove R13/R14 and see the table on the schematic.
Allows selection of the A0 I2C address bit. The EVM default is set to address 1000000 by R13/R14.
For other address options remove R13/R14 and see the table on the schematic.
Selecting the S1 EN position (toward TP15) allows the TPS2480/1 to enable the MOSFET if the
power bus input is above the turn on voltage. Setting S1 away from the EN position disables the
MOSFET.
For manufacturing use only. Shunts must remain installed in J11 and J12.
Table 3. Test Points
Label
Description
+IN
Power bus input high.
–IN
Power bus input low.
+OUT
Switched bus output high.
–OUT
Switched bus output low.
SNS
SNS pin test point.
GATE
GATE pin test point.
PG
PG pin (power good) test point.
TMR
TMR pin (timer) test point.
PRG
PROG pin (power program) test point.
EN
EN pin (enable) test point.
SCL
SCL pin (serial clock) test point.
SDA
SDA pin (serial data) test point.
A1
A1 pin (upper address bit) test point. Level set by R14 and J9.
A0
A0 pin (lower address bit) test point. Level set by R13 and J10.
3P3V_USB
VS pin (current monitor supply voltage) test point. The USB source applied at J13 powers
the current monitor.
GND
GNDB pin (current monitor ground) test point. The USB source applied at J13 powers the
current monitor.
HSNS
High-voltage (HV) sense test point. TPS2480/1EVM-001 provides a circuit to shift the current
monitor input. This test point mirrors the voltage at TP1.
LSNS
Low-voltage (LV) sense test point. This test point represents the HV to LV mirrored current
sense voltage.
V–
Sense voltage mirror negative supply voltage. Normally ~5 V below the power bus high-input
voltage.
USB
USB active indicator LED. When a USB power source is presently connected to a PC, this
LED illuminates.
Copyright © 2010, Texas Instruments Incorporated
General Configuration and Description
Table 3
describes the test point availability.
TPS2480 and TPS2481 Evaluation Module
3
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