General Configuration And Description; Physical Access - Texas Instruments TPS23525EVM-815 User Manual

General Configuration and Description

3 General Configuration and Description
3.1

Physical Access

Table 2 lists the TPS23525EVM connector and functionality,
and Table 4 describes the default jumper configuration.
Connector
J1, J2, J3
J7 Neg48V_B
J8 Vout_FLTD
J9
J10 Neg48V_A
Connector
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13, TP15
TP14 Neg48VB
TP16 HS_DRAIN
TP17 VOUT_FLTD
TP18 Neg48VA
TP19
Connector
J5 Jump pins 1-2 to enable UV (default), or jump pins 2-3 to tie UV to VCC (disable)
J6 Leave open to enable OV (default), or jump pins 1-2 to tie OV to GND (disable)
4
TPS23525EVM-815 Evaluation Module
Table 2. Connector Functionality
Label
RTN Power bus input - Tie the high-side of power-supply inputs and outputs here
Power bus input - Tie the low-side of power-supply B input here
Output bus - Apply the low-side load here (if applicable)
CAUX Connect to auxiliary bulk capacitor (if applicable)
Power bus input - Tie the low-side of power-supply A input here
Table 3. Test Points
Label
RTN High-side power-supply input and high-side output load voltage
VCC Clamped voltage supply
PGB Power Good Bar
SS Soft-start pin voltage
UVEN UV pin voltage
D D pin voltage
OV OV pin voltage
GATE Gate drive output voltage for hot-swap FET
SNS Sense pin test point
TMR Timer capacitor voltage
GATEB Gate drive output voltage for Gate B ORing FET
GATEA Gate drive output voltage for Gate A ORing FET
VEE IC ground - Place voltage probe ground at this pin
Low-side input for power-supply B
Drain voltage of the hot-swap FET
Low-side output for load
Low-side input for power-supply A
- Open-drain output for power good signal. Attach to downstream EN pin.
Table 4. Jumper Descriptions
Copyright © 2017, Texas Instruments Incorporated
Table 3 describes the test point availability,
Description
Description
Description
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SLVUB36 – October 2017