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3.2 10-way JTAG header - non-standard pin-out
This connection method is suitable for interfacing the programmer to a Target System which is
programmed via the 'JTAG' interface.
Important note:
This is a non-standard pin-out and so is not directly compatible with any standard JTAG
connector for e.g AVR or ARM devices. A custom wired cable will be required.
Pin
Programmer
No
Pin name
1
TARGET_VCC
2
BUFFER_ENABLE
3
Programmer I/O4
4
Programmer I/O1
5
RELAY ENABLE
6
Programmer I/O2
7 + 9 PROG_GND
8
Programmer I/O3
10
PROG_RESET/VPP
Key
O - Output from programmer to Target Device
I - Input to programmer from Target Device
52
Figure 3.1- Equinox 10-way IDC Header (J7) viewed from above
Warning!
Connecting to the wrong ISP Header may cause
catastrophic damage to the Programmer & Target System
Connect to
I/O
pin on
Target System
P
TARGET_VCC
Connect to Clock Buffer
IO5
circuit Buffer Enable pin
IO4 - O JTAG – TMS
IO1 - I JTAG – TDI
Controlled output used to
O
switch external relay
IO2 - O JTAG - TDO
P
Signal GROUND (0V)
IO3 - O
JTAG - SCK
O
RESET
ISPJUNO - Portable ISP Programmer - User Guide V0.84 – 17/04/20
Target VCC
This pin should be connected to the
Target System Vcc.
This pin is used to enable the
output of a remote Clock Buffer.
JTAG - Test Mode Select
JTAG - Test Data IN
Direct programmer output with 470
ohm resistor in series. Requires
external transistor to drive relay.
JTAG - Test Data OUT
Signal Ground Connection (1)
0V to which the programmer JTAG,
SPI, I2C signal lines are referenced
to.
SPI Clock
Target RESET control pin
This pin controls the Target Device
RESET pin.
P - Passive e.g. GROUND and power rails
N/C - Not connected
Notes
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