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TPMC634-10R
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Manuals and User Guides for Tews Technologies TPMC634-10R. We have
1
Tews Technologies TPMC634-10R manual available for free PDF download: User Manual
Tews Technologies TPMC634-10R User Manual (93 pages)
Re-Configurable FPGA with 64 TTL I/O / 32 Differential I/O
Brand:
Tews Technologies
| Category:
I/O Systems
| Size: 1 MB
Table of Contents
Table of Contents
4
1 Product Description
9
Figure 1-1 : Tpmc634 Block Diagram
10
2 Technical Specification
11
Table 2-1 : Technical Specification
12
3 Handling and Operation Instructions
13
ESD Protection
13
User FPGA Power Dissipation Limit
13
I/O Interface Installation
13
Default TTL I/O Line States
13
Pre-Installed User FPGA Example
14
4 Pci Target Interface
15
PCI Configuration Space (PCI Header)
15
Figure 4-1 : Pci Header
15
PCI BAR Overview
16
Table 4-1 : Tpmc634 Pci Bar Overview
16
PCI Configuration EEPROM Parameter
17
Table 4-2 : Pci Configuration Eeprom Map
17
PCI Access Times
18
PCI Clock Frequency
18
Table 4-3 : Approximate Pci Access Times
18
5 Address Maps
19
PCI Target Register Space
19
Table 5-1 : Pci Target Register Space
19
Local Bus Interface Register (0X90)
20
Configuration EEPROM Register (0Xb0)
21
Table 5-2 : Local Bus Interface Register
21
Table 5-3 : Configuration Eeprom Register
21
Interrupt Enable Register (0Xc0)
22
Table 5-4 : Interrupt Enable Register
22
Interrupt Status Register (0Xc4)
23
Table 5-5 : Interrupt Status Register
23
Interrupt Configuration Register (0Xc8)
24
Table 5-6 : Interrupt Configuration Register
24
User FPGA Configuration Control/Status Register (0Xd0)
24
Table 5-7 : User Fpga Configuration Control/Status Register
25
Table 5-8 : User Fpga Configuration Data Register (Slave Selectmap)
25
User FPGA Configuration Data Register (Slave Selectmap) (0Xd4)
25
ISP Command Register (SPI) (0Xe8)
26
ISP Configuration Register (SPI) (0Xe4)
26
ISP Control Register (SPI) (0Xe0)
26
Table 5-10: Isp Configuration Register (Spi)
26
Table 5-9 : Isp Control Register (Spi)
26
ISP Status Register (SPI) (0Xec)
27
Table 5-11: Isp Command Register (Spi)
27
Table 5-12: Isp Status Register (Spi)
27
Control & Status Register (0Xf0)
28
Firmware Version Register (0Xfc)
28
In-System Programming Space
28
Table 5-13: Dip-Switch Register
28
Table 5-14: Version Register
28
Table 5-15: User Space Overview
29
User Space(S)
29
6 User Programmable Fpga
30
FPGA Part
30
I/O Bank Supply & Supported I/O Standards
30
User FPGA I/O Signal & Pin Description
30
Local Bus Interface Signals
30
Table 6-1 : User Fpga Resources
30
I/O Interface Signals
32
Table 6-2 : Local Bus Interface Signals (Fpga Parameters)
32
Table 6-3 : I/O Interface Signals (Fpga Parameters)
38
Table 6-4 : Fpga I/O Interface Signal Description
38
Table 6-5 : Fpga I/O Interface Signal Usage for Tpmc634 Variants
39
Other User Signals
40
Reserved FPGA I/O Pins
40
Table 6-6 : Other User Signals
40
User FPGA Power Dissipation Limit
41
Table 6-7 : Reserved Fpga I/O Pins
41
7 User Programmable Fpga Configuration
42
User FPGA Configuration Options
42
FPGA Configuration from SPI Flash
42
Auto-Configuration at Power-Up
42
SW Controlled Re-Configuration
42
SPI Flash Preparation
43
FPGA Configuration Time
43
Table 7-1 : Estimated Fpga Configuration Time
43
FPGA Configuration Via Pci/Software
44
Configuration Data Files
44
Direct FPGA Programming
46
FPGA Configuration Via JTAG Header
47
8 Spi Flash Programming
49
SPI Flash Notes
49
SPI Flash Device Type
49
SPI Flash Programming Options
49
SPI Flash Non-Volatile QE Bit
49
Xilinx ISE / Bitgen Options
50
SPI Flash Programming Via Pci/Software
50
SPI Flash Program Data
50
SPI Flash Instructions
51
Steps for SPI Flash Chip Erase Operation
51
Steps for SPI Flash Program Operation
52
Steps for SPI Flash Sector Erase Operation
52
Steps for SPI Flash Read Operation
53
Steps for Setting the SPI Flash Non-Volatile QE Bit
54
SPI Flash Programming Via JTAG Header
55
MCS Programming File Generation
55
SPI Flash Programming
57
9 Local Bus Interface
62
Local Bus Interface Notes
62
Local Bus Cycle Description
62
Local Bus Master Abort (Local Bus Time-Out)
63
Local Bus Target Error
63
Local Bus Signal Description
64
Local Bus Interface Timing
66
Table 9-1 : Local Bus Signal Description
66
Table 9-2 : Local Bus Interface Timing
66
Local Bus Signal Protocol Example Diagrams
67
Figure 9-1 : Local Bus Signal Protocol Example Diagrams
68
10 Interrupts
69
Interrupt Sources
69
Interrupt Handling
69
SPI Flash In-System Programming Interrupts
69
Local Bus User Interrupt
70
Local Bus Error Interrupt
70
11 Leds
71
Figure 11-1: Led Location
71
Table 11-1: On-Board Leds
71
12 Jtag Header
72
Figure 12-1: Jtag Header Pin Order
72
Table 12-1: Jtag Header Part Number
72
Table 12-2: Jtag Header Pin Assignment
72
Figure 12-1: Jtag Header Location
73
13 Board Hw-Configuration
74
Readable DIP-Switch
74
TTL I/O Pull-Resistor Reference
74
Table 13-1: 4-Pos. Rotary Switch Configuration
74
14 O Interface
75
General I/O Interface Description
75
Single-Ended I/O Line Interface
75
Figure 14-1: Single-Ended I/O Line Interface
76
Differential I/O Line Interface
77
Figure 14-2: Differential I/O Line Interface
77
Figure 14-3: Front Panel I/O Connector Numbering
78
Front-I/O Connector Part Number
78
I/O Connectors
78
I/O Line Signal Level
78
Rear-I/O Connector Part Number
78
Table 14-1 : Front I/O Connector Part Number
78
Table 14-2: Rear I/O Connector Part Number
78
Table 14-3: I/O Line Signal Level
78
Front-I/O Pin Assignment
79
Table 14-4: Tpmc634 Front I/O Pin Assignment
79
Rear-I/O Pin Assignment
80
Table 14-5: Tpmc634 Rear I/O Pin Assignment
80
15 Appendix A: User Fpga Port Map
81
16 Appendix B: User Fpga Constraint File
82
17 Appendix C: Pre-Installed User Fpga Example Application
89
User FPGA Example Register Map
89
User FPGA Example Register Description
90
PMC I/O Input Register (Lower) (0X00)
90
PMC I/O Input Register (Upper) (0X04)
90
PMC I/O Output Register (Lower) (0X08)
90
Table 17-1 : User Fpga Example Register Map
90
Table 17-2: Pmc I/O Input Register (Lower) (0X00)
90
Table 17-3: Pmc I/O Input Register (Upper) (0X04)
90
PMC I/O Output Register (Upper) (0X0C)
91
PMC I/O Output Enable Register (Lower) (0X10)
91
PMC I/O Output Enable Register (Upper) (0X14)
91
PMC I/O Rising Edge Interrupt Enable Register (0X20)
91
Table 17-4: Pmc I/O Output Register (Lower) (0X08)
91
Table 17-5: Pmc I/O Output Register (Upper) (0X0C)
91
Table 17-6: Pmc I/O Output Enable Register (Lower) (0X10)
91
Table 17-7: Pmc I/O Output Enable Register (Upper) (0X14)
91
Table 17-8: Pmc I/O Rising Edge Interrupt Enable Register (0X20)
91
PMC I/O Falling Edge Interrupt Enable Register (0X24)
92
PMC I/O Interrupt Status Register (0X28)
92
Clock Counter Control Register (0Xe0)
92
Table 17-9: Pmc I/O Falling Edge Interrupt Enable Register (0X24)
92
Table 17-10: Pmc I/O Interrupt Status Register (0X28)
92
Table 17-11: Clock Counter Control Register (0Xe0)
92
Clock Counter Register - Local Bus Clock (0Xe4)
93
Clock Counter Register - Auxiliary Clock (0Xe8)
93
Clock Counter Register - Baud Rate Clock (0Xec)
93
General R/W Test Register (0Xf8)
93
Version Register (0Xfc)
93
Table 17-12: Clock Counter Register - Local Bus Clock (0Xe4)
93
Table 17-13: Clock Counter Register - Auxiliary Clock (0Xe8)
93
Table 17-14: Clock Counter Register - Baud Rate Clock (0Xec)
93
Table 17-15: General R/W Test Register (0Xf8)
93
Table 17-16: Version Register (0Xfc)
93
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