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4.0 Basic Operation
4.1 Initialization
The PE11S100X synthesizer does not maintain register states after power down. After power is supplied
to the PE11S100X synthesizer modules, all registers should be loaded with the appropriate values. Default
values for these registers can be found in section 7.1 Register Map on page 22, with instructions for
performing the serial data write operations found in 5.2 Serial Port WRITE Operation on page 15.
4.2 Frequency Tuning
f
= f
VCO
Where:
N
is the integer division ratio, between 36 and 65531 in fractional mode
int
between 32 and 65535 in integer mode
N
is the functional division ratio between 0 and 2
frac
f
is the frequency of the reference (f
REF
input frequency.
M
is the prescaler coefficient for the particular synthesizer
As an example, for a synthesizer with M = 2 and f
Hz is achieved using N
=00E6h = 0000 0000 1110 0110 into dsm_intg in
= 0000 0000 0000 0000 0000 0001 into dsm_frac in
In integer mode the synthesizer step size is fixed to M times phase frequency detection (PFD) the reference
frequency, f
. Integer mode typically has lower phase noise for a given reference frequency than fractional
REF
mode. In integer mode the digital Δ Σ modulator is normally shut off. To run in integer mode set
dsm_integer_mode
(Reg 12
of the frequency, N
, as explained by
int
operation in integer mode would result in a frequency of 4600 MHz.
4.3 Frequency Hopping
If the synthesizer is in fractional mode, a write to the fractional frequency register.
frequency hop on the falling edge of the 31st clock edge of the serial port write (see
If the integer frequency register,
and only executed when the fractional frequency register is written.
If the synthesizer is in integer mode, a write to the integer frequency register, Reg 0Fh, will initiate the
frequency hop on the falling edge of the 31st clock edge of the serial port write (see
© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc.
f
•
REF
N
M +
•
•
REF
int
= 230 and N
= 1. These are set by programming the 6-bit binary value of 230d
int
frac
h<3>) and clear dsm_rstb
(EQ
Reg
0Fh, is written when in fractional mode, the information will be buffered
N
M
•
frac
2
24
-1
24
/R), where f
REFIN
REFIN
= 10 MHz, the output frequency of 4,600,000,001.19
REF
Reg
0Fh. Similarly the 24 bit binary value of 1d = 000001h
Reg 10
h.
(Reg
01h<13>). Then program the integer portion
1), ignoring the fractional part. From the above example,
(EQ 1)
is the reference
Reg 10h
will initiate the
Figure
5).
Figure
5).
9
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