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User Manual | PE11S100X Series Synthesizer
7.16 Reg 0Eh Reserved
Bit
Type
23:0
R/W
Reserved
7.17 Reg 0Fh Integer Division Register
Bit
Type
15:0
R/W
dsm_intg
7.18 Reg 10h Fractional Division Register
Bit
Type
23:0
R/W
dsm_frac
7.19 Reg 11h Speed Register
Bit
Type
23:0
R/W
dsm_seed
7.20 Reg 12h Delta Sigma Modulator Register
Bit
Type
0
R/W
dsm_ref_clk_select
1
R/W
dsm_invert_clk_sd3
2
R/W
dsm_invert_clk_rph
3
R/W
dsm_integer_mode
4
R/W
Reserved
5
R/W
Reserved
6
R/W
dsm_xref_sin_select
7
R/W
dsm_autoseed
24
Name
Default
0
Name
Default
400
Name
Default
0
Name
Default
3A1953h
Name
Default
0
0
1
0
0
0
1
1
Description
Reserved
Description
unsigned integer portion of VCO divider value,
also known as NINT, see EQ 1
Description
unsigned integer portion of VCO divider value,
also known as NFRAC, see EQ 1
Description
unsigned seed value for ΔƩ modulator sets the
start phase of the modulator
Description
use reference instead of divider
invert ΔΣ clk
inverts the ref clock phase
1- enables Integer Mode, bypasses the ΔΣ
modulator, leaves it running
see also dsm_rstb Reg01h<13> to disable the
modulator
when xref is selected specifies that the sine
source is used
automatic seed load when changing the frac
part, uses value in seed
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