User Manual | PE11S100X Series Synthesizer User Environment This instrument is designed for indoor use only. Revision Control Revision Description of Changes Date Initial Creation 08/18/2011 Pasternack Updates 05/13/2019 Acronyms Phase Lock Loop SCPI Standard Commands for Programmable Instrumentation pasternack.com...
User Manual | PE11S100X Series Synthesizer 1.0 Applicable Products PE11S1001, PE11S1002 2.0 General Description This operating guide applies to the PE11S100X synthesizer modules operating up to 20 GHz output frequency. The purpose of this guide is to describe features common to all the synthesizer modules. The PE11S100X synthesizer modules contain phase locked loops consisting of various Pasternack die.
User Manual | PE11S100X Series Synthesizer 4.4 CW Sweeper Mode The internal PLL features a built-in frequency sweeper function, useful for test instrumentation, FMCW sensors, automotive radars, and other applications. Sweeper modes include: a. Single-Step Ramp Mode b. 1-Way Sweep Mode c.
User Manual | PE11S100X Series Synthesizer Figure 3. 2-Way Sweep Control via Trigger 4.4.3 Single Step Ramp Mode Single-step mode is selected by setting ramp_singlestep (Reg 14 h<6>). In this mode, a trigger is required for each step of the ramp. Single-step mode will function with either one-way or two-way ramps. The operation of single-step mode for a one-way ramp is shown graphically in Figure Figure 4.
User Manual | PE11S100X Series Synthesizer DC leakage or “offset” may be added to the UP or DN pumps using cp_UPoffset_sel and cp_DNoffset_sel 08h). These are 4 bit registers with 28.7 μA LSB. Maximum offset is 430 μA. (Reg As an example, if the main pump gain was set at 1 mA, an offset of 373 μA would represent a phase offset of about (392/1000)*360 = 133 degrees 4.5.4 Charge Pump Operation Near the Minimum &...
User Manual | PE11S100X Series Synthesizer the pin is exclusively SDO. If automux is enabled, the pin switches to SDO when the RD function is sensed on the 1st rising edge of SCK. If lkd_to_sdo_always is set, then the pin LD is dedicated for Lock Detect only, and it is not possible to read from the synthesizer.
Page 18
User Manual | PE11S100X Series Synthesizer With this simplification the single sideband integrated VCO phase noise, Ф , in rads at the phase detector is given by where π (EQ 2) ) / N is the single sideband phase noise in rads /Hz inside the loop bandwidth, B is the 3-dB corner frequency of the closed loop PLL, and N is the division ratio of the prescaler.
User Manual | PE11S100X Series Synthesizer Figure 9. Normal Lock Detect Window 6.4 Lock Detect with Phase Offset When operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. The phase detector linearity is worse when operated with zero phase offset. Hence in fractional mode it is necessary to offset the phase of the reference and the VCO at the phase detector.
User Manual | PE11S100X Series Synthesizer 7.5 Reg 03h Reserved Type Name Default Description rfp_div_ratio, also 13:0 referred to as “R” 16:14 Reserved Reserved 7.6 Reg 04h Prescaler Duty Cycle Register Type Name Default Description Extends the low time from 15 to 47 VCO cycles vcop_dutycycmode for large divide ratios 7.7 Reg 05h Reserved...
User Manual | PE11S100X Series Synthesizer 7.16 Reg 0Eh Reserved Type Name Default Description 23:0 Reserved Reserved 7.17 Reg 0Fh Integer Division Register Type Name Default Description unsigned integer portion of VCO divider value, 15:0 dsm_intg also known as NINT, see EQ 1 7.18 Reg 10h Fractional Division Register Type Name...
User Manual | PE11S100X Series Synthesizer 7.24 Reg 16h CW Sweep Ramp Step Number Register Type Name Default Description 23:0 ramp_steps_number 2048 Ramp Number of steps in ramp 7.25 Reg 17h CW Sweep Dwell Time Register Type Name Default Description Ramp Number of cycles to hold at top/bottom in 23:0 ramp_dwell_time...
User Manual | PE11S100X Series Synthesizer x1x = disable GPO2 pad driver 1xx = disable GPO3 pad driver 7.30 Reg 1Ch Phase Detector CSP Register Type Name Default Description 0= Cycle Slip Prevention (CSP) disabled 4-bit value to advance or retard phase detector pfds_sat_deltaN in VCO cycles if it reaches 2pi, i.e.