Reg 1Bh Gpo Control Register - Infinite Pasternack PE11S100 Series User Manual

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16:15
R/W
lkd_ringosc_cfg
18:17
R/W
lkd_monost_duration
19
R/W
lkd_ringosc_testmode

7.29 Reg 1Bh GPO Control Register

Bit
Type
gpo_sel
gpo_sel<3:0> = 0000
gpo_sel<3:0> = 0001
gpo_sel<3:0> = 0010
gpo_sel<3:0> = 0011
gpo_sel<3:0> = 0100
3:0
R/W
gpo_sel<3:0> = 0101
gpo_sel<3:0> = 0110
gpo_sel<3:0> = 0111
gpo_sel<3:0> = 1000
gpo_sel<3:0> = 1001
gpo_sel<3:0> = 1010
6:4
R/W
gpo_sel_0_data
7
R/W
gpo_dig_drive_en
Chip ID 478732
Reserved
10:8
R/W
Chip ID 481502
gpo_ind_drive_dis
© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc.
3
3
0
Name
Default
0
0
1
0
0
"0" fastest "3" slowest
"0" shortest "3" longest
enables the ring osc by itself for testing
Description
Selects data to be driven on GPO ports
GPO3 <=gposel_0_data<2> GPO2 <=
gposel_0_data<1> GPO1 <= gposel_0_data<0>
GPO3 <= xref_clk_in GPO2 <= ref_clk_in GPO1
<= vco_div_clkin
GP03 <= pfd_up_in GP02 <= pfd_dn_in
GP01 <= LKD_monost_window
GP03 <= pfd_sat_ref_in GP02 <=
pfd_sat_vco_div_in
GP01 <= delta_integer_cycslip_sel, this strobe
holds the gain of the PFD at max for anti-cycle
slipping
GP03 <= xref_clk_in GP02 <= xref_sin_in
GP01 <= sd_frac_strobe_sync, internally
synchronized frac strobe
VCO Serial Port Mirror GPO3 - VSDO
GPO2 = VSCK
GPO1 = SVLE
GP03 <= SD_Intz1<1> GP02 <=SD_Intz1<2>
GP01 <= SD_Intz1<3>
3-bit quantized version of the VCO phase
GP03 <= aux_clk GP02 <= ringosc_test GP01
<= clk_SD
GP03 <= 00
GP02 <= ramp_busy GP01 <= vcot_busy
Not used
GP03 <= Δ∑ Quantizer Output 3rd lsb GP02 <=
Δ∑ Quantizer Output 2nd lsb GP01 <= Δ∑
Quantizer Output lsb
this data is driven on gpo if gpo_sel==0
enables Tri-state drivers on GPO output pads
reserved must write 0 on Chip ID 478732
Chip ID 481502 Only
000 = all GPO pad drivers enabled xx1 = disable
GPO1 pad driver
27

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