Advanced Operation; Cycle Slip Prevention (Csp) - Infinite Pasternack PE11S100 Series User Manual

User Manual | PE11S100X Series Synthesizer
the pin is exclusively SDO. If automux is enabled, the pin switches to SDO when the RD function is sensed
on the 1st rising edge of SCK. If lkd_to_sdo_always is set, then the pin LD is dedicated for Lock Detect
only, and it is not possible to read from the synthesizer.
A typical READ cycle is shown in Figure 6.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed by
a rising edge SCK
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI high initiates the READ
cycle (RD)
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave reads the address bits on the next six rising edges of SCK (2-7).
e. Slave places the 24 data bits on the next 24 rising edges of SCK (8-31), MSB first.
f. Host reads the data bits on the next 24 falling edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCK.
h. The 32nd falling edge of SCK completes the cycle
Figure 6. Serial Port Timing Diagram – READ

6.0 Advanced Operation

6.1 Cycle Slip Prevention (CSP)

When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD
varies rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with
phase up to ±2π, the gain of conventional PFDs will cycle from high gain, when the phase difference
approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0
radians. This phenomena is known as cycle slipping. Cycle slipping causes the pull-in rate during the
locking phase to vary cyclically as shown in the red curve in Figure 7. Cycle slipping increases the time to
lock to a value far greater than that predicted by normal small signal Laplace analysis.
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