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User Manual | PE11S100X Series Synthesizer
7.24 Reg 16h CW Sweep Ramp Step Number Register
Bit
Type
23:0
R/W
ramp_steps_number
7.25 Reg 17h CW Sweep Dwell Time Register
Bit
Type
23:0
R/W
ramp_dwell_time
7.26 Reg 18h Reserved
Bit
Type
22:0
R/W
Reserved
7.27 Reg 19h Reserved
Bit
Type
4:0
R/W
Reserved
7.28 Reg 1Ah Lock Detect Register
Bit
Type
9:0
R/W
lkd_wincnt_max
10
R/W
lkd_win_asym_enable
11
R/W
lkd_win_asym_up_select
12
R/W
lkd_to_sdo_automux_en
13
R/W
lkd_to_sdo_always
14
R/W
lkd_ringosc_mono_select
26
Name
Default
2048
Name
Default
2048
Name
Default
144
Name
Default
15
Name
Default
298
0
0
1
0
0
Description
Ramp Number of steps in ramp
Description
Ramp Number of cycles to hold at top/bottom in
repeat mode
Description
Reserved
Description
Reserved
Description
threshold count in the timer window to declare
lock (reference cycles)
Enables asymmetric lock detect window
(nominal 10nsec)
Sets polarity of the window
Muxes the lkd output signal to SDO when SDO
is not being used for Main Serial Port Data
Outputs (Read Operation)
Muxes the lkd output signal to SDO always, not
possible to do Main Serial Port Read in this
state
1 select ringosc based oneshot for lock detect
window
0 selects analog based oneshot
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