Serial Port Write Operation; Main Serial Port Read Operation - Infinite Pasternack PE11S100 Series User Manual

5.1 Serial Port WRITE Operation

Table 1. Timing Characteristics
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
A typical WRITE cycle is shown in
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low initiates the
Write cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave reads the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f. Slave reads the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCK.
h. The 32nd falling edge of SCK completes the cycle.
Figure 5. Serial Port Timing Diagram - Write Serial Port WRITE Operation

5.2 Main Serial Port READ Operation

The synthesizer uses the multi-purpose pin, LD, for both Lock Detect and Serial Data Out (SDO) functions.
The registers lkd_to_sdo_automux_en
how the Data Output pin is muxed with the Lock Detect function. If both of the registers are cleared, then
© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc.
Conditions
SEN to SCK Setup Time
SDI to SCK Setup Time
SDI to SCK Hold Time
SCK High Duration
SCK Low Duration
SEN High Duration
Figure 5.
(Reg 1Ah<12>) and lkd_to_sdo_always
Min Typ Max
8
10
10
8
8
640
(Reg 1Ah<13>) determine
Units
nsec
nsec
nsec
nsec
nsec
nsec
15