Reg 03H Reserved; Reg 04H Prescaler Duty Cycle Register; Reg 05H Reserved; Reg 06H Phase Freq Detector Delay Register - Infinite Pasternack PE11S100 Series User Manual

User Manual | PE11S100X Series Synthesizer

7.5 Reg 03h Reserved

Bit Type
rfp_div_ratio, also
13:0 R/W
referred to as "R"
16:14 R/W Reserved

7.6 Reg 04h Prescaler Duty Cycle Register

Bit Type
0 R/W vcop_dutycycmode

7.7 Reg 05h Reserved

Bit Type
2:0 R/W Reserved

7.8 Reg 06h Phase Freq Detector Delay Register

Bit Type
2:0 R/W pfd_del_sel

7.9 Reg 07h Charge Pump UP/DN Control Register

Bit Type
4:0 R/W cp_UPcurrent_sel
9:5 R/W cp_DNcurrent_sel
7.10 Reg 08h Charge Pump Trim & Offset Register
Bit Type
3:0 R/W cp_UPtrim_sel
7:4 R/W cp_DNtrim_sel
22
Name Default
1
7
Name Default
1
Name Default
7
Name Default
2
Name Default
16
16
Name Default
0
0
Description
Reserved
Description
Extends the low time from 15 to 47 VCO cycles
for large divide ratios
Description
Reserved
Description
Delay line setpoint to PFD
Description
Sets Charge-Pump Up gain, 125 μA lsb, binary,
4 mA max
Sets Charge-Pump Dn gain, 125 μA lsb, binary,
4 mA max
Description
Trim Up gain, 14.3μA lsb, binary, 100μA max
Trim Dn gain, 14.3μA lsb, binary, 100μA max
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