VIA Technologies Zida BX983D User Manual page 36

Mainboard Installation
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you enable/disable the PCI #2 Access #1 Retry.
The choice: Enabled, Disabled.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.
PCI IRQ Activated by
This sets the method by which the PCI bus recognizes that an IRQ service is being requested by a device.
Under all circumstances, you should retain the default configuration unless advised otherwise by your
system's manufacturer.
Choices are Level (default) and Edge.
Assign IRQ For USB/VGA/ACPI
Name the interrupt request (IRQ) line assigned to the USB/VGA/ACPI (if any) on your system. Activity of
the selected IRQ always awakens the system.
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