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OUT
Current state of counter output
NC
Null count is 1 when the last count written to the counter
register has been loaded into the counting element
The counter enable register, located at address BASE+10, has a close
relationship with the counter operation. Refer to Chapter 4, Timer/
counter enable register, for the register data format. The TC0 bit
enables and disables the pacer. If TC0 = 0, the pacer is enabled. If
TC0 = 1, the pacer is disabled and trigger pulses from the pacer are
kept from the A/D until TRIG0 is taken high. The TC1 bit controls the
input source for Counter 0. If TC1 = 0, Counter 0 is configured to
accept external clock pulses. If TC1 = 1, Counter 0 is internally
connected to the 100 KHz clock source.
The output will be initially low after this mode of operation is set.
After you load the count into the selected count register, the output
will remain low and the counter will count. When the counter reaches
the terminal count, its output will go high and remain high until you
reload it with the mode or a new count value. The counter continues to
decrement after it reaches the terminal count. Rewriting a counter
register during counting has the following results:
1. Writing to the first byte stops the current counting.
2. Writing to the second byte starts the new count.
The output is initially high. The output will go low on the count
following the rising edge of the gate input. It will then go high on the
terminal count. If you load a new count value while the output is low,
the new value will not affect the duration of the one-shot pulse until
the succeeding trigger. You can read the current count at any time
without affecting the one-shot pulse. The one-shot is retriggerable,
thus the output will remain low for the full count after any rising edge
at the gate input.
Chapter 8 Programmable counter/timer
53
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