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JP2 controls the input clock frequency for the 8254 programmable
clock/timer. You have two choices: 10 MHz and 1 MHz. This lets you
generate pacer output frequencies from 2.5 MHz to 0.00023 Hz
(71 minutes/pulse).
The following equation gives the pacer rate:
Fclk is 1 MHz or 10 MHz as set by jumper JP2. Div1 and Div2 are the
dividers set in counter 1 and counter 2 in the 8254. See Chapter for
more information on the card's 8254 counter/timer.
JP3 has two jumpers. The upper jumper selects the card's A/D trigger
source when you use external triggering. The lower jumper selects the
gate control for counter 0 of the card's 8254 timer/counter.
You have two choices: DI0 (pin 1) on connector CN2 or TRIG0 (pin
35) on CN3.
You have two choices: DI2 (pin 3) on connector CN2 or GATE0 (pin
36) on CN3.
12
PCL-818L User's Manual
Pacer rate = Fclk / ( Div1 * Div2 )
10 MHz
1M
10M
TRIG0
DIO
TRIG0
GATE0
DI2
GATE0
1 MHz (default)
1M
10M
DI0 (default)
DIO
TRIG0
DI2 (default)
DI2
GATE0
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