Technical Data - YASKAWA VIPA System 200V Manual

Manual VIPA System 200V

Technical data

214-2BS03
HB97E - CPU - RE_21x-2BS03 - Rev. 15/16
Order no.
Type
Technical data power supply
Power supply (rated value)
Power supply (permitted range)
Reverse polarity protection
Current consumption (no-load operation)
Current consumption (rated value)
Inrush current
I²t
Max. current drain at backplane bus
Power loss
Load and working memory
Load memory, integrated
Load memory, maximum
Work memory, integrated
Work memory, maximal
Memory divided in 50% program / 50% data
Memory card slot
Hardware configuration
Racks, max.
Modules per rack, max.
Number of integrated DP master
Number of DP master via CP
Operable function modules
Operable communication modules PtP
Operable communication modules LAN
Command processing times
Bit instructions, min.
Word instruction, min.
Double integer arithmetic, min.
Floating-point arithmetic, min.
Timers/Counters and their retentive
characteristics
Number of S7 counters
S7 counter remanence
S7 counter remanence adjustable
Number of S7 times
S7 times remanence
S7 times remanence adjustable
Data range and retentive characteristic
Number of flags
Bit memories retentive characteristic adjustable
Bit memories retentive characteristic preset
Number of data blocks
Max. data blocks size
Number range DBs
Max. local data size per execution level
Max. local data size per block
Blocks
Number of OBs
Maximum OB size
Total number DBs, FBs, FCs
Number of FBs
Maximum FB size
Number range FBs
Chapter 2 Hardware description
214-2BS03
CPU 214SER
DC 24 V
DC 20.4...28.8 V
90 mA
1.5 A
65 A
0.75 A²s
3 A
5 W
144 KB
144 KB
96 KB
96 KB
-
MMC-Card with max. 512 MB
4
total max. 32
-
8
32
32
-
0.18 µs
0.78 µs
1.8 µs
40 µs
256
adjustable 0 up to 64
C0 .. C7
256
adjustable 0 up to 128
not retentive
8192 Bit
adjustable 0 up to 256
MB0 .. MB15
2047
16 KB
1 ... 2047
1024 Byte
1024 Byte
14
16 KB
-
1024
16 KB
0 ... 1023
2-7