Layout And Electromagnetic Compatibility; General; Power Line Routing - Fujitsu ALL FR 460 Series Application Note

FR460 Hardware Set Up
Chapter 2 Layout and Electromagnetic Compatibility

2 Layout and Electromagnetic Compatibility

THIS CHAPTER GIVES SOME TIPS FOR LAYOUT DESIGN

2.1 General

To avoid ESD problems and noise emission of the system some rules for the layout design
has to be observed.
The most critical point is the C pin because this is the connection to the internal 3.3V supply
for the MCU core. Thus a decoupling capacitor has to be placed very near to this pin.
Also the ground and VDD routing has to be done carefully. VDD lines should be routed in star
shape. We recommend a VSS ground plane on the mounting side just under the MCU. For
both VDD and VSS only one connection to the rest of the circuit should be done, otherwise
noise is carried-over from and to the MCU. Decoupling capacitors (DeCaps) has to be placed
as nearest as possible to the related pins. If they are placed too far away their function
becomes useless.
If crystals are used, they have to be placed as nearest as possible to the X1(A) pins.
If possible all decoupling capacitors should be placed on the same mounting side as the MCU.

2.2 Power Line Routing

In general the VDD and VSS lines should not be routed in "chains", but in "star shape". For
VSS a ground plane is recommended which covers the chip package, and is connected in one
point to VSS of the whole circuit.
Below is a example of a bad and a good power line routing:
© Fujitsu Microelectronics Europe GmbH - 9 - MCU-AN-300033-E-V13