Architecture Without Dual I/O Link Redundancy; Architecture With Dual I/O Link Redundancy - Honeywell ML200 Series Installation And Commissioning Manual

Chapter 3 - Plan and Install MLPLC
Both CPU modules must have the same version of the operating system.
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The configuration of both the CPU modules must be in the same sequence. For example: If
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2MLL-EFMT is installed in the slot 0 of CPU-A, 2MLL-EFMT in the CPU-B must be installed
in the slot 0.

Architecture without dual I/O link redundancy

The cable connection for ML200R without dual I/O link redundancy is as follows:
Connect the synchronization cable between Master and Standby CPUs
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Synchronization cable: Tx to Rx, Rx to Tx (Multi-mode FO, LC connector type)
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Connect the expansion cable between I/O racks and CPUs in a Ring Configuration
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UTP cable: Direct or Cross cable (Cross cable is recommended)
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Fiber Optic cable: Tx to Rx, Rx to Tx (Multi-mode FO, LC connector type)
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The following image illustrates the ML 200R architecture without dual I/O link redundancy.
Figure 15: ML200R architecture without dual I/O link redundancy

Architecture with dual I/O link redundancy

The cable connection for ML200R with dual I/O link redundancy and is as follows:
Connect the synchronization cable between Master and Standby CPUs
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Synchronization cable : Tx to Rx, Rx to Tx (Multi-mode FO, LC connector type)
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Connect the expansion cable between I/O racks and CPUs in a Ring Configuration
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UTP cable : Direct or Cross cable (Cross cable is recommended)
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