Port Input/Output; Figure 12.1. Port I/O Functional Block Diagram; Figure 12.2. Port I/O Cell Block Diagram - Silicon Laboratories C8051F300 Manual

12. Port Input/Output

Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins
can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital
resources as shown in Figure 12.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 12.3 and Figure 12.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 12.1, SFR
Definition 12.2, and SFR Definition 12.3 are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 12.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port0 Output Mode register (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Table 12.1 on page 110.
Highest
Priority
Lowest
Priority

Figure 12.1. Port I/O Functional Block Diagram

/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
ANALOG INPUT
PORT-INPUT
2
UART
2
SMBus
2
CP0
Outputs
SYSCLK
4
PCA
2
T0, T1
8
Port Latch P0
(P0.0-P0.7)
Analog Select

Figure 12.2. Port I/O Cell Block Diagram

C8051F300/1/2/3/4/5
XBR0, XBR1, P0MDOUT,
XBR2 Registers P0MDIN Registers
Priority
Decoder
Digital
Crossbar
P0
8
I/O
Cells
VDD VDD
GND
Rev. 2.9
P0.0
P0.7
(WEAK)
PORT
PAD
103