Silicon Laboratories C8051F300 Manual page 44

C8051F300/1/2/3/4/5
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2)
R/W R/W
AD0EN AD0TM
Bit7 Bit6
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read: Unused.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2-0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of '1' to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
1xx: ADC0 conversion initiated on rising edge of external CNVSTR.
When AD0TM = 1:
000: Tracking initiated on write of '1' to AD0BUSY and lasts 3 SAR clocks, followed by con-
version.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conver-
sion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conver-
sion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conver-
sion.
1xx: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
44
R/W R/W R/W
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
Bit5 Bit4 Bit3
Rev. 2.9
R/W R/W R/W
Bit2 Bit1 Bit0
(bit addressable)
Reset Value
SFR Address:
0xE8