Silicon Laboratories C8051F300 Manual page 43

SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2)
R/W R/W
AD0SC4 AD0SC3 AD0SC2
Bit7 Bit6
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
SYSCLK
--------------------- - 1
AD0SC =
CLK
Bit2: UNUSED. Read = 0b; Write = don't care.
Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2)
R/W R/W
Bit7 Bit6
Bits7–0: ADC0 Data Word.
ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended
mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2's
complement signed 8-bit integer.
R/W R/W R/W
AD0SC1 AD0SC0
Bit5 Bit4 Bit3
–
SAR
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 2.9
C8051F300/1/2/3/4/5
R/W R/W R/W
— AMP0GN1 AMP0GN0 11111000
Bit2 Bit1 Bit0
R/W R/W R/W
Bit2 Bit1 Bit0
Reset Value
SFR Address:
0xBC
Reset Value
00000000
SFR Address:
0xBE
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