Silicon Laboratories C8051F300 Manual page 168

C8051F300/1/2/3/4/5
R/W R/W
CIDL WDTE
Bit7 Bit6
Bit7: CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bit6: WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the Watchdog Timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Bit5: WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Bit4: UNUSED. Read = 0b, Write = don't care.
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the clock source for the PCA counter
CPS2 CPS1
0
0
0
0
1
1
1
1
*Note: External oscillator source divided by 8 is synchronized with the system clock.
Bit0: ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt when CF (PCA0CN.7) is set.
Note: When the WDTE bit is set to '1', the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
168
SFR Definition 16.2. PCA0MD: PCA Mode
R/W R/W R/W
WDLCK — CPS2
Bit5 Bit4 Bit3
CPS0
0 0 System clock divided by 12
0 1 System clock divided by 4
1 0 Timer 0 overflow
1 1 High-to-low transitions on ECI (max rate = system clock
divided by 4)
0 0 System clock
0 1 External clock divided by 8
1 0 Reserved
1 1 Reserved
Rev. 2.9
R/W R/W R/W
CPS1 CPS0 ECF
Bit2 Bit1 Bit0
Timebase
*
Reset Value
01000000
SFR Address:
0xD9