Glossary - Fujitsu PRIMEPOWER850 User Manual

100Base-TX
An IEEE standard. Applicable cable types are
unshielded twisted-pair (UTP) and shielded
twisted-pair (STP). Applicable connector type
is RJ45. Allows bandwidth of 100 Mbps, and
the maximum segment length is 100 m (328 ft).
10Base-T
An IEEE standard. Applicable cable type is
unshielded twisted-pair (UTP), and the
connector type is RJ45. Allows bandwidth of
10 Mbps, and the maximum segment length is
100 m (328 ft).
Branch Prediction
Branching occurs after the CPU evaluates a
conditional command, or after it receives an
external input (interrupt). Normally, data is fed
to the CPU in order of execution, but a branch
means that the instructions that have already
been fed into the pipeline have to be flushed,
and the CPU must wait for the required
instructions to be loaded before it can proceed.
In extreme cases this can be a considerable
drain on performance, so rather than blindly
feeding data to the CPU in order of reception, if
the presence of upcoming potential branches is
noted, data can be preloaded into the cache, and
each branch followed by the sequence of
instructions calculated as being most likely to
be called after the branch. Of course sometimes
the prediction will be wrong and data will still
have to be flushed and reloaded, but the more
accurate the prediction, and the better the
preloading, the lower the performance penalty
becomes.
U41261-J-Z816-4-76

Glossary

Bus (Line)
A path (circuit, signal line, etc.) or set of paths
that is capable of transferring a signal, usually
between components within the system (e.g.
CPU memory) or a system component and a
peripheral device
(e.g. CPU hard disk).
Bus Protocol
The (predefined) logical structure and timing of
the signals that are passed over a bus.
Cache (Primary or L1 Cache)
In order to prevent a fast CPU from having to
wait for access to the relatively slow external
memory, a small amount of very fast memory is
often included within the CPU itself, and
frequently used data and instructions are stored
in this level one (L1) cache memory.
Cache (Secondary or L2 Cache)
Although very fast, L1 cache is also very
expensive, and it is often impractical to add
large amounts of it to the CPU design.
However, it is relatively easy to add more fast
memory close to, but not in the CPU, and this
level two (L2) cache memory, while slower
(and usually larger) than the L1 cache, is faster
than the main memory, for improved system
performance.
Checksum
A hash value calculated (e.g. using parity) in
some way from a set of data, and then appended
to it or compared with a previously appended
checksum in order to validate the integrity of
the data set (after transmission, retrieval from
storage, etc.). Basically, even the most minor
change to the data will produce a different
checksum value, hence an error can be flagged
if the calculated and transmitted/retrieved
checksum values do not match.
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