National Instruments PXI Express Series User Manual page 23

Chapter 1 Getting Started
By default, a high-level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge the
PXIe_SYNC100 signal will restart. This will allow several chassis to have
their PXIe_SYNC100 in phase with each other. Refer to Figure 1-7 for
timing details with this method.
NI PXIe-1062Q User Manual
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PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
Figure 1-7. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
1-14
SYNC100 Divider
Restarted Here
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