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Advanced Chipset
Control Sub-Menu
DRAM Speed:
DMA Aliasing:
8-bit I/O Recovery:
16-bit I/O Recovery:
IRQ 12 used by:
ECC/Parity Config:
Chapter 3
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This sub-menu allows you to control selected settings for the chipset that
affect performance or function. The Advanced Chipset Control Sub-Menu
is shown below.
PhoenixBIOS Setup - Copyright 1985-95 Phoenix Technologies Ltd.
Advanced
Advanced Chipset Control
DRAM Speed:
DMA Aliasing:
8-bit I/O Recovery:
16 bit I/O Recovery:
IRQ12 used by:
ECC/Parity Config:
↑ ↓ Select Item
F1
Help
← → Select Menu
ESC Exit
Figure 3-9. Advanced Chipset Control Sub-Menu
This field sets the speed of the installed DRAM SODIMMs. Selecting 70 ns
for 60 ns SODIMMs decreases performance. Selecting 60 ns for 70 ns
SODIMMs is invalid. The default is 60ns.
This field allows I/O accesses to the range 90-9FH (except 92H) to alias to
80-8FH. If an ISAbus device uses the address range 90-9FH, then this field
must be disabled to access the device. The default is Enabled.
This field selects the number of ISAbus SYSCLKs to be inserted by the
chipset between 8-bit back-to-back I/O accesses. Increasing the number of
clocks decreases I/O performance but may allow slow devices to be
accessed properly. Values can range from 3.5 through 11.5 SYSCLKs, in
1 SYSCLK increments. The default is 4.5 SYSCLKs.
This field selects the number of ISAbus SYSCLKs to be inserted by the
chipset between 16-bit back-to-back I/O accesses. Increasing the number of
clocks decreases I/O performance but may allow slow devices to be
accessed properly. Values can range from 3.5 through 7.5 SYSCLKs, in
1 SYSCLK increments. The default is 4.5 SYSCLKs.
This field selects the routing of IRQ12. For systems without a PS/2 mouse,
this field may be set to ISA bus to allow an ISAbus peripheral to use this
interrupt line. Systems using a PS/2 mouse must have this field set to PS/2
Mouse (the default) for the mouse to operate correctly.
This field configures the DRAM controller to use no parity (Disabled),
parity (Parity), or Error Checking and Correction (ECC) when accessing
DRAM. Use of parity or ECC may improve system reliability since DRAM
errors are likely to be detected by the chipset. Use of ECC allows for the
detection of single and dual bit errors and the correction of single bit errors
during DRAM reads. The parity and ECC selections require that all
SODIMMs be x36 instead of x32. The no parity (disabled) selection can use
Item Specific Help
[60ns]
<Tab>, <Shift-Tab>, or
<Enter> selects field.
[Enabled]
[4.5]
[4.5]
[PS/2 Mouse]
[Disabled]
-/+
Change Values
F9
Enter Select > Sub-Menu F10 Previous Values
Using the BIOS Setup Utility
Setup Defaults
37
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