Protocol Registers (8148H And 8149H); Response Registers (814Ah And 814Bh) - RadiSys EPC - 6A Hardware Reference Manual

Protocol Registers (8148h and 8149h)

Protocol Register, lower
Protocol Register, upper
This read-only register is defined by the VXIbus specification. In VXI systems, it defines
the EPC-6A as being a servant and commander, having no signal register, being a bus
master, and not providing fast handshake mode.

Response Registers (814Ah and 814Bh)

Response Register, lower
Response Register, upper
With the exception of LOCK, this register is defined by the VXIbus specification. It
contains control bits associated with the message registers.
LOCK
ABMH
ULAULA Unique logical address. This determines the base of the registers in the
RRDY
WRDY
Although the intention is that the message register reads and writes that clear WRDY and
RRDY come from another VMEbus processor, accesses to the message register as mapped
into the EPC-6A's I/O space also have the same effect.
When the response register is read from the VMEbus, the current value of the register is
read, and then LOCK is cleared. The protocol for sending a message to the EPC-6A, if
there are multiple potential senders, is the following. The sender first reads the response
register. If both WRDY and LOCK are 1, he may then proceed to send the message. For a
16-bit message, the sender writes into the message-low register. For a 32-bit message, he
writes first into the message-high register and then the message-low register.
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1
0
LOCK
0
If set, the message register can be locked for the sending of a message. If clear,
the message register is locked.
This bit is cleared when the message high register is read or written. It serves
as a location monitor for determining whether a message is 16 or 32 bits in
length.
VMEbus A16 space. 0 denotes FE00, 1 denotes FE40, 2 denotes FE80, 3
denotes FEC0, 4 denotes FF00, 5 denotes FF40, 6 denotes FF80, and 7 denotes
FFC0.
Read ready. As defined by VXI, a 1 denotes that the message registers contain
outgoing data to be read by another device. RRDY is cleared when the message
low register is read.
Write ready. If set, the message registers are armed for an incoming message.
When a write occurs into the message-low register, WRDY is cleared and the
MSGR interrupt condition is asserted.
Appendix C: Registers
1 1 1 1
1 0 1 1
1 ABMH 1 1
0 0 0 1 RRDY WRDY
1 1 1
1 1 1
ULA
1
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