Vmebus Interrupt Handler - RadiSys EPC - 6A Hardware Reference Manual

EPC-6A Hardware Reference
When the 486DX2 performs a locked access (for example, via an instruction using the
LOCK instruction prefix) to the local DRAM, VMEbus slave accesses are held up until
the last locked access completes.

VMEbus Interrupt Handler

Although software available for the EPC-6A shields the user from the details of interrupt
handling, the following information is provided for the reader who needs further detail.
The relationship between VME interrupts (and other interrupt-causing events) and an
interrupt as seen by a program is shown in the following diagram.
Interrupts and events are visible in two state registers. These are unlatched, meaning that a
read of the state register shows the actual state of the signals at the instant of the read. The
exception is BERR, which is a "sticky" bit, meaning that the bit signifies whether BERR
had ever been asserted. The convention used is that a 0 bit signifies an asserted
(interrupting) state.
The primary purpose of the state registers is to let the interrupt handler software determine
which interrupts and events generated the IRQ10 interrupt to the processor. The state
registers can also be read by non-interrupt-handler software to poll for the state of these
signals.
The enable registers allow one to mask selectively these 12 states. A 0 state bit and a
corresponding 1 enable bit causes the PC architecture IRQ10 interrupt to be asserted.
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RRDY
WRDY
IRQ1
IRQ2
IRQ3
VMEbus
interrupts
IRQ4
IRQ5
IRQ6
IRQ7
SYSFAIL
BERR (sticky)
ACFAIL
WDT
VME VME
interrupt interrupt
state enable
register register
M
A
S
K
M
A
S
K
VME VME
event event
state enable
register register
PC
architecture
IRQ10