Vmebus Interrupt Response - RadiSys EPC - 6A Hardware Reference Manual

Unlike the 12 input conditions, which are level sensitive inputs, the PC architecture
defines the PC interrupts, such as IRQ10, as edge sensitive. This requires special attention
if you are writing your own interrupt handlers (for example, if you are not using the
functions in the Bus Manager software). Because IRQ10 is edge triggered, you could miss
an incoming interrupt/event that occurs when IRQ10 is disabled, meaning that your
software needs to test for and handle all pending interrupts/events before you leave from
the IRQ10 interrupt handler. To do this correctly, follow the following steps. These steps
assume the reader is familiar with the programming of the 8259 interrupt controller in the
PC architecture.
1. When the IRQ10 interrupt occurs, acknowledge the interrupt by sending
end-of-interrupt to both 8259 interrupt controllers.
2. Depending on your environment, you may wish to switch to another stack (a must
under DOS), and may wish to save the state of the VME modifier and address
registers if you will be using them.
3. To prevent reentry to the interrupt handler, mask off all the interrupts/events or mask
off the IRQ10 interrupt. (Reenable what you have masked off at the end of the
interrupt handler.)
4. Find an enabled pending interrupt/event.
5. If an enabled pending VMEbus interrupt is found, do an interrupt-acknowledge cycle
by setting the IACK bit in the VME modifier register and performing a VMEbus read,
setting address bits A3–A1 to denote the interrupt number. This returns the status/ID
value from the interrupter. For the other controllable conditions (message, sticky
BERR, watchdog timer), you may follow the instructions earlier in this chapter to
remove these interrupting conditions.
6. Perform application-dependent handling of the interrupt/event.
7. If there are still enabled pending interrupts/events, go to step 4. If not, return from the
IRQ10 interrupt handler.

VMEbus Interrupt Response

When the EPC-6A's interrupt generator register is used to assert an interrupt, the EPC-6A
formulates a status/ID value that is transmitted on the bus as the response to a matching
interrupt acknowledgeInterrupt:acknowledgement cycle. The EPC-6A acts as both a
D08(O) and D16 interrupter. For D08 interrupt acknowledge cycles, the status/ID value is
the EPC-6A's logical address (11111aaa, where aaa is the value of ULA as defined in port
814A). For D16 interrupt-acknowledge cycles, the status/ID value consists of 16 bits. The
upper eight bits are the upper half of the response register (the value in I/O port 814B) and
the lower eight bits are the logical address.
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Chapter 4: Programming Interface
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