Vmebus Interface; Vmebus System Controller Functions - RadiSys EPC - 6A Hardware Reference Manual

EPC-6A Hardware Reference

VMEbus Interface

The EPC-6A connects to the VMEbus J1 connector. All of the VMEbus signals and
voltages on this connector are used except for SERCLK, SERDAT, and +5V STDBY.
The EPC-6A, when configured as an A24 slave, responds with BERR if another bus
master attempts a D32 access into the EPC-6A's memory. It also responds with BERR if
another master does an access that would map to other than DRAM within the EPC-6A.
The EPC-6A does address pipelining in one circumstance—when the EPC-6A has been
granted the bus while some other master is performing a bus cycle. In this circumstance
the EPC-6A will start its cycle (for example, drive AS* low) before the other master has
removed its data strobes (for example, before DS0* and DS1* are driven high).
The EPC-6A performs write pipelining of 486 write cycles to the VMEbus. The VME
control logic signals completion to the 486 of a write cycle that is mapped to the VMEbus
as soon as the VMEbus AS* signal has been driven low and the data from the 486 has
been latched.

VMEbus System Controller Functions

When the EPC-6A is configured as the VMEbus system controller, it performs the
standard VMEbus system controller functions. It serves as the bus arbiter (priority or
round robin), drives the 16 MHz SYSCLK signal, and starts the IACK daisy chain.
The SYSFAIL LED is operable only when the EPC-6A is configured as the system
controller.
When configured as the system controller, the EPC-6A also detects and terminates bus
timeouts. Once it sees either of the DS0 and DS1 lines asserted, a counter is started. If the
counter expires before both DS0 and DS1 are deasserted, the EPC-6A asserts the VMEbus
BERRsignal until both data strobes are deasserted. The duration of the counter is
approximately 100 microseconds.
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