Module Status/Control Register (8156H); Interrupt Generator Register (815Fh); Fsa Address Registers 8380H) - RadiSys EPC - 6A Hardware Reference Manual

EPC-6A Hardware Reference

Module Status/Control Register (8156h)

Module Status/Control Reg
This register contains miscellaneous status and control bits.
DONE
AS
DS0
DS1
FWDT
A write to the module status/control register also has a side effect of resetting the
watchdog timer. Therefore, if you are using the watchdog timer, the intention is that you
are required to write to this register within the defined period of the timer to prevent its
generating an interrupt or reset.

Interrupt Generator Register (815Fh)

Interrupt Generator Register
This register is used to assert one of the VMEbus interrupt signals. If the
INTERRUPT-OUT bits are zero, no interrupt line is asserted by the EPC-6A. If set to 001,
IRQ1 is asserted. If set to 010, IRQ2 is asserted, and so on. If and when an interrupt
acknowledge is sent to the EPC-6A, the INTERRUPT-OUT bits are cleared.
You can also deassert a previously asserted interrupt by writing 0 into the register.

FSA Address Registers 8380h)

FSA7–0 Address Register
FS A15–8 Address Register
FS A19–16 Address Register
These read/write registers specify the address of the byte to be accessed within the flash or
SRAM array when the data register is accessed. Since the SRAM has software support for
only 32 KB, the 15 low-order address bits are pertinent to it.
60
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DONE
This read-only bit is 0 whenever the EPC-6A has a VMEbus access
outstanding. It is used for determining when a pipelined VMEbus write is
complete.
This read-only bit is 1 whenever the VMEbus AS (address strobe) signal is
asserted. It may be used for bus monitoring.
This read-only bit is 1 whenever the VMEbus DS0 (data strobe) signal is
asserted. It may be used for bus monitoring.
This read-only bit is 1 whenever the VMEbus DS1 (data strobe) signal is
asserted. It may be used for bus monitoring.
Fast watchdog timer. If clear, the period of the watchdog timer is
approximately 8 seconds. If set, the period is approximately 250 ms.
1
AS DS0 DS1 res
1 1 1 0
Flash/SRAM address bits 7–0
Flash/SRAM address bits 15–8
reserved Flash/SRAM address bits 19–16
res FWDT ENRE
INTERRUPT-OUT