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MPU
C3
HORIZONTAL
A VERTICAL
SIGNALS
ADDRESS _ _ _ _ _ _ _ _
PLAYFIELD
RAM
BUS_-.........-..
AO-A9
I
<1>2---_J
F3,H3,J3,K3
F4,H4,J4,K4
_..,___-/
ADDR
8-BIT
LATCH
FS,LS
CLK
<1>2
DISPLAY 0-5
4V
2V
1V
(ADDR
3-8)
DOUT
PLAYFIELD
ROM
P4,R4
ADDR2
ADDR1
ADDRO
8-BIT
SHIFT
REGISTER
R3
PLAYFIELD VIDEO
(TO VIDEO SUMMING
CIRCUIT)
Figure 3-10 Playfield Generator Block Diagram
E. PLAYFIELD GENERATOR
(See Figure 3-3, Sheet 4 of 5)
The playfield generator generates both the al-
phanumeric and playfield data for the TV monitor
display. The video is actually generated by graphics
ROMs P4 and R4 and 8-bit shift register R3. See Figure
3-10.
Which alphanumeric or playfield characters are
to be displayed and where on the screen they are to
be placed is controlled by the MPU Display RAM (F4,
H4, J4, K4, F3, H3, J3, K3). To unde.rstand how MPU-
generated data in the display RAM controls place-
ment of these characters, it is first necessary to un-
derstand the organization of the playfield display it-
self. The playfield is structured as a 32 x 32 matrix,
consisting of 32 horizontal rows of characters-each
row being32 characters wide. (Actually, only28 of the
32 rows of characters are visible on the screen, since
3 -10 Super Breakout
the bottom four rows are blanked out by the V
BLANK* signal during the vertical blanking and re-
trace period.) Each character is structured as an 8 x 8
block, eight lines high with eight bits of data per line.
See Figure 3-11.
Since there are 32 rows of characters, with 32
characters per row, there are a total of 1,024 (32 x 32)
positions in which to place a character. The display
RAM consists of the eight I Cs mentioned above. Each
of these chips is a memory size of 1,024 addresses,
with one bit of data per address. When all eight of
these RAMs are considered as a group,they have a
memory size of 1,024 x 8.
Because of the unique way in which the game
circuitry is structured, each of 1,024 addresses in the
display RAM corresponds to one of the 1,024 possible
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