Mpu, Rom, And Ram; Address Decoding; L>O Clock Qriver - Atari Super Breakout Operation, Maintenance And Service Manual

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The functional operation of the Super Breakout
PCB circuitry begins naturally enough with the mi-
croprocessor (or MPU) circuitry. As you go through
the various circuit descriptions, you learn how the
MPU receives its sequential program insructions
from its ROM memory and how it carries out these
instructions through the use of its display RAM mem-
ory (Section C); how it reads in the game control
switches (Section G), and how it writes or outputs the
results of its instructions and calculations to the
game's other PCB circuitry, such as the playfield
generator (Section E), the motion object generator
(Section F), and the audio amplifier (Section K).
A circuit description of the standard Atari sync
generator (Section D) is also included. This is the only
PCB circuitry that functions independently of micro-
processor control.
B. POWER SUPPLY
(See Figure 3-3, Sheet 1 of 5 and
Figure 3-5)
The power supply produces all the necessary
game voltage requirements as shown in Figure 3-4.
The PCB receives
+10
volts DC, unregulated, at
pins B and 2 of the game PCB edge connector;
16.5 VAC to pins C and 3 and D and 4; and 25 VAC to
pins Wand 19 and X and 20 from the secondary of the
transformer located on the Type B power supply
chassis.
The +10 volts is rectified and filtered off-board
and regulated on-board by the LM323 three-terminal
regulator device to a stable +5 volts DC. The +5 volts
DC is distributed throughout the PCB to power all
logic circuits. The 16.5 VAC is rectified on-board via
diodes CR1 and CR2, filtered by capacitor C54 before
being regulated by the 7905 to produce the -5 volts
DC, required by the voltage comparator, LM319. The
25 VAC input is rectified through diodes CR3 and CR4
filtered by capacitor C55 and supplied as unregulated
+20 volts to the TDA 1004 audio amplifier. This +20
volts is also regulated by a three-terminal device 7B12
(QB) to develop +12 volts DC.
C. MICROPROCESSOR CIRCfilTRY
(See Figure 3-3, Sheet 2 of 5)
The heart of the Super Breakout game PCB is the
microprocessor circuitry. A brief description of the
3-4
Super Breakout
major components and their function within the mi-
croprocessor circuitry is provided in the following
paragraphs. Note that the microprocessor circuitry
components include the following:
1. MPU (at location C3)
2. Address buffers (A2, 82 and C2)
3. Data buffers (E3, E4)
4. ROM memory (C1, D1 and E/F1) for -04 version or
PROM memory as listed in the PCB assembly parts
list for the -03 version (refer to Illustrated Parts
Catalog, Section 5).
5. RAM memory (F4, H4, J4, K4, F3, H3, J3, and K3)
6. Address decoding circuitry (E2, F2, D2, EB, and HB,
and miscellaneous gates)
7. <l>O clock driver (A7 and miscellaneous gates)
B. Watchdog reset counter (C6/7 and miscellaneous
gates)
MPU, ROM, and RAM (See Figure 3-5)
The microprocessor is the "master controller"
behind all action that takes place in the game cir-
cuitry. In going through the following paragraphs
refer to Table 3-1, MPU Input/Output Signal De-
scriptions. Upon initialization, the MPU (via AO-A15)
addresses data permanently stored in the program
ROMs or PROMs. This addressed data then travels to
the MPU via its B-bit data bus (DO through D7). The
MPU decodes this data to determine what action it is
to perform next (i.e., "read coin switch 1," "ball
speed up," etc.). The MPU uses RAM memory to
perform many of these instructions, namely to
tempo_rarily store information which it will later re-
call. The MPU is capable of writing (or putting data
into) the RAM and then later reading (pulling data out
of) the RAM, via its address bus (AO-A15) and bi-
directional data bus (DO-D7).
Address Decoding
The MPU address decoding circuitry performs
the critical function of turning on or enabling the
appropriate game circuitry (i.e., RAM, ROM, latches,
etc.) at the appropriate time, so that information can
be transferred back and forth between this game
circuitry and the MPU. A memory map defining the
MPU circuit is shown in Table 3-2 as reference.

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