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,---
1
+10VDC
(UNREGULATED)
B/2
GAME
+5VDC
LOGIC
(REGULATED)
,::sou~
I
I
I
POWER
SUPPLY
CHASSIS
C/3
16.5 VAC,....,
D/4
PCB
POWER
SUPPLY
REGULATOR
CIRCUITS
-5VDC
TO PADDLE CIRCUITRY
(REGULATED)
COMPARATOR
+ 20
voe
TO AUDIO AMP
FROM ADDRESS
MULTIPLEXERS
K2, J2, H2
BUFFERED
DATA BUS
TO
MPU
CHIP
C3
TO
BIDIRECTIONAL
MPU DATA BUS
(UNREGULATED)
25 VAC ,....,
X/20
+12
voe
L_ _ _ _
_J
(REGULATED)
Figure 3-4 Power Supply Simplified Block Diagram
RAM
CIRCUITRY
READ/WRITE
MEMORY
(1024x1 BIT
RAM CHIPS)
RAM MEMORY BLOCK DIAGRAM
8-BIT
LATCH
(F5)
TRI-STATE
(ES, KS)
TO DISPLAY
ROM,
~
DISPLAY
_ _ ..,, DISPLAY 0-7
J;,,..i_
.
- - -
MOTION
CIRCUITS,
AND SOUND
GENERATOR
D0-7,,_/______
BILATERAL
~
TOMPU
____ _,
'
DATA BUS
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
~ADR0-9
BUFFERED
ADDRESS
ROM
PROGRAM
MEMORY
1 - - - - - - - 1 1
(3 ROM CHIPS)
-04VERSION
PROM/ROM
Figure 3-5 Memory Block Diagram
EITHER/OR
ROM 2, ROM 3, ROM 4 ENABLE
<l>O Clock Driver (See Figure 3-6)
ana <1>2 (pins 3 and 39) waveforms with an oscillo-
scope should show two signals of opposite polarity
with a period of 1.33 microseconds. (The period
ofany periodic waveform is the measurement of the
time it takes to complete one full cycle.) The 750 kHz
clock frequencies are derived from the 4H signal. This
The basic operating frequency of the micropro-
cessor is established by its <l>O input (on pin 37 of the
MPU device). The Super Breakout MPU runs at an
operating frequency of 750 kHz. Examination of <M
Super Breakout
3-5
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