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16H
32H
64H
1
L
128H
~
~------
63.5 MILLISECONDS
~I
256H
------....JMI~--
PLAYFIELD DISPLAY
;;l_
HBLANK
-
HSYNC
-
Figure 3-8 Horizontal Sync Timing Diagram
av
16V
32V
64V
J
L
L
128V
~---------------
16.3 MILLISECONDS
l.-
4
~
VB LANK
~------
PLAYFIELD DISPLAY
- - - - - - - - - - - 1 ..
..i-
VB LANK
-----------------------------
VSYNC
I
VRESET
•
Figure 3-9
Vertical Sync Timing Diagram
frequencies (1V through 128V). These two
stages of vertical counters are used, in effect, to
do a divide by 262 of the H SYNC signal. This
results in the final output of these counters
(128V at pin 11 of M3) to be a signal at a fre-
quency of 60 Hz (the period is approximately
16.3 milliseconds). The various vertical fre-
quencies address a sync PROM (M2) whose
output data is latched by latch N2. The outputs
of this latch are the various polarities and phases
of the vertical timing frequency used to syn-
chronize the TV monitor display. These signals
all run at a frequency of 60 Hz. See Figure 3-10,
Vertical Sync Timing Diagram for the relative
timing of these waveforms.
The end result of the horizontal and vertical
timing waveforms is to synchronize the TV
monitor display (COMP SYNC*). This display
consists of 262 horizontal lines per frame, with
each line being the time equivalent of 768
12 MHz clock pulses. Each frame is repeated 60
times per second, providing the necessary fre-
quency of display refresh that provides a stable
non-flickering display.
Super Breakout 3-9
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