Configuring Nrzi Format - Cisco 7000 Series Hardware Installation And Maintenance Manual

Installing and Configuring Processor Modules
Setting the Clock Rate
All DCE interfaces require a noninverted internal transmit clock signal, which is generated by the
FSIP. The default operation on an FSIP DCE interface is for the DCE device (FSIP) to generate its
own clock signal (TxC) and send it to the remote DTE. The remote DTE device returns the clock
signal to the DCE (FSIP port). When using DCE interfaces, you must connect a DCE-mode adapter
cable to the port and specify the rate of the internal clock with the clockrate configuration command
followed by the bits-per-second value. In the following example, the first serial interface on an FSIP
in interface processor slot 2 (2/0) is defined as having a clock rate of 2 Mbps.
Following are acceptable clockrate settings:
1200, 2400, 4800, 9600, 19200, 38400, 56000, 64000, 72000, 125000, 148000, 500000, 800000,
1000000, 1300000, 2000000, or 4000000
Speeds above 64 kbps (64000) are not appropriate for EIA/TIA-232; use EIA/TIA-449 on faster
interfaces. Note that the faster speeds might not work if your cable is too long. If you change an
interface from DCE to DTE, you can use the no clockrate command to remove the clock rate
although it is not necessary to do so. The port automatically recognizes the DTE cable and ignores
the clock rate until a DCE cable is attached to the port again.
The FSIP ports support full duplex operation at DS1 (1.544 Mbps) and E1 (2.048 Mbps) speeds.
Each four-port module (see the section "Fast Serial Interface Processor (FSIP)" in the chapter
"Product Overview") can support an aggregate bandwidth of 6.132 Mbps.
Because each four-port module shares a processor, you can delegate bandwidth to a single port and
leave the other ports idle to optimize speed and bandwidth on a single interface. For example, you
can configure four T1 interfaces on a module (one T1 on each port) such that they do not exceed
6.132 Mbps, or you can configure one port to operate at up to 6.132 Mbps, and leave the remaining
three ports shut down. The type of electrical interface, the amount of traffic processed, and the types
of external data service units (DSUs) connected to the ports affect actual rates.
Inverting the Clock Signal
Systems that use long cables may experience high error rates when operating at the higher speeds.
Slight variances in cable length, temperature, and network configuration can cause the data and
clock signals to shift out of phase. Inverting the clock can often correct this shift. The
invert-transmit-clock configuration command inverts the TxC clock signal for DCE interfaces.
This prevents phase shifting of the data with respect to the clock. To change the clock back to its
original phase, use the no invert-transmit-clock command. In the example that follows, the clock
is inverted for the first serial port on an FSIP in interface processor slot 2:

Configuring NRZI Format

The default for all interface types is for nonreturn to zero (NRZ) format; however, all types also
support nonreturn to zero inverted (NRZI). NRZ encoding is most common. NRZI encoding is used
primarily with EIA/TIA232 connections in IBM environments. To enable NRZI encoding on any
5-48 Cisco 7010 Hardware Installation and Maintenance
7010# configure terminal
interface serial 2/0
clockrate 2000000
^z
7010# configure terminal
interface serial 2/0
invert-transmit-clock
^z