Power Supply Circuits - Icom ID-800H Service Manual

• V-VCO CIRCUIT
The oscillated signal at the V-VCO circuit (Q3, D1, D2) is
amplified at the buffer amplifier (Q4), and is then applied to
the LO switch (D5, D6). The receive 1st LO (Rx) signal from
the LO switch (D6) is passed through the low-pass filter (L7,
L8, C36–C38), and is then applied to the 1st mixer circuit
(MAIN unit; Q32). The transmit signal from the LO switch (D5)
is applied to the pre-drive amplifier (MAIN unit; Q30).
A portion of the amplified signal from the buffer amplifier (Q4)
is amplified at the buffer amplifier (Q50) via the VCO switch
(D50), and is then fed back to the PLL IC (MAIN unit; IC1,
pin 8) as the comparison signal.
• U-VCO CIRCUIT
The oscillated signal at the U-VCO circuit (Q101, D100,
D101) is amplifi ed at the buffer amplifi er (Q102, Q103), and
is then applied to the LO switch (D103–D105).
While operating UHF band (EXP: 430–440 MHz, USA: 440–
450 MHz), the receive 1st LO signal (Rx) is passed through
the LO switch (D104) and low-pass fi lter (L105, L106, C126)
and then applied to the 1st mixer circuit (MAIN unit; Q35)
via the VCO switch (D106). The transmit signal is passed
through the LO switch (D103) and low-pass filter (L104,
C122, C124), and then applied to the pre-drive amplifier
(MAIN unit; Q31).
While receiving 400 MHz band signals (230–550 MHz
except UHF band), the output signal from the LO switch
(D104) passes through the low-pass filter (L105, L106,
C126), and is then applied to the 1st mixer circuit (MAIN
unit; IC12) via the VCO switch (D106).
While receiving 800 MHz band signals (810–1000 MHz),
the output signal from the LO switch (D105) is doubled at
the doubler (Q104), and passes through the bandpass filter
(L108–L110, C127, C129, C132, C133, C135). The signal
is applied to the 1st mixer circuit (MAIN unit; IC12) via the
VCO switch (D107).
• UHF PLL CIRCUIT
Loop
filter
X1
15.2 MHz
UHF VCO
Buffer
Q101, D100, D101
Phase Programmable
15
detector counter
Programmable
divider
1
A portion of the amplified signal from the buffer amplifier
(Q102) is amplified at the buffer amplifier (Q50) via the VCO
switch (D51), and is then fed back to the PLL IC (MAIN unit;
IC2, pin 8) as the comparison signal.
4-4

POWER SUPPLY CIRCUITS

4-4-1 CONTROL UNIT VOLTAGE LINE
Line
Common 5 V converted from the HV line at the
+5V regulator circuit (IC5, D4). The output volt-
CPU5V
age is applied to the sub CPU (IC16) and reset
IC (IC2).
Common 8 V converted from the HV line at the
8 V regulator circuit (Q1, Q3, D5). The output
8V voltage is applied to the LCD backlights (DS22,
DS23) and key backlights (DS13–DS18, DS20,
DS21) circuit.
4-4-2 CODEC UNIT VOLTAGE LINE
Line
Common 5 V controlled by the +5 V regulator
5V circuit (Q50 and Q51) using the "PSAVE" signal
from the CODEC CPU (IC204, pins 58, 59).
Common 3.3 V converted from the 5V line by the
3.3V
3.3V regulator circuit (IC1).
Common 3.2 V converted from the 8 V line by
the 3.2V regulator circuit (IC2). The circuit is con-
3.2V
trolled by the "APWR" signal from the CODEC
CPU (IC204, pin 16).
LO switch
Q103
Buffer
Q102
VCO
switch
Buffer
Q50
D51
IC2 MB15A02PFV1
Prescaler
Shift register
4 - 8
Description
Description
D103
to the transmitter circuit
D104
to the 1st mixer circuit
LPF
D105
BPF
2
Q104
8
9
PLLCK
10
PLLDATA
11
PLLSTB2