Lattice Semiconductor MachXO2 Series Usage Manual page 5

Table 3. SED Attributes
Attribute Name
SED_CLK_FREQ
DEV_DENSITY
CHECKALWAYS
The SED_CLK_FREQ attribute is used to specify the clock frequency. The SEDFA primitive uses the MachXO2
internal oscillator as the clock source. The available settings are those shown in Table 2. If a value other than those
shown in the table is used the software will issue an error message and exit from the MAP process.
The DEV_DENSITY attribute is used to specify the device density for the MachXO2 simulation model. If the
DEV_DENSITY attribute is not specified the default value of 1200L will be used. The allowable values for the
DEV_DENSITY attribute are:
256L, 640L, 1200L, 2000L, 4000L, 7000L, 640U, 1200U, or 2000U
The CHECKALWAYS attribute is not supported at this time.
Port Descriptions
SEDENABLE
SEDENABLE is a level-sensitive signal which enables SED checking when high. When this signal is low, the SED
hardware is disabled. This can be tied high in a design if desired.
SEDSTART
SEDSTART is the signal which starts the SED process. The rising edge of the SEDSTART signal will cause the
SED cycle to start if SEDENABLE is high. The SEDSTART signal must remain high until the SED process has
completed. If SEDSTART goes low during the SED cycle the process will be terminated without asserting SED-
DONE or SEDERR.
SEDFRCERR
SEDFRCERR is used to force the SED process to return an error indication on the SEDERR signal. This is typi-
cally done to test the logic associated with the SEDERR output. The rising edge of the SEDFRCERR signal is
detected by the SED hardware and latched in by the rising edge of the SED Clock Driver signal. The SEDFRCERR
should be latched high while the SED is active for an error indication to be returned. The recommended use is for
the user logic to drive the SEDFRCERR signal from low to high once the rising edge of the SEDINPROG signal is
detected and while following the setup/hold time requirements defined in Figure 5.
SEDSTDBY
The SEDSTDBY port is provided on the SEDFA primitive only and must be connected to the SEDSTDBY output
port on OSCH component. This signal is provided for simulation support of the STDBY function which can be used
to turn off the internal oscillator. When the STDBY function turns off the internal oscillator the SEDFA block will no
longer operate because its clock source has been turned off. If the user does not connect this signal on the SEDFA
primitive the SED will still function the same way in the hardware but may not match the simulation results when
STDBY is used.
SEDCLKOUT
SEDCLKOUT is a gated version of the SED Clock Driver signal to the SED block. SEDCLKOUT is gated by SED-
ENABLE. This signal can be used to synchronize the inputs to the SED block or the outputs from the SED block.
Attribute Type
String Specifies the clock frequency when used with SEDFA primitive.
String Specifies the device density for use by the simulation model.
String Reserved for future use.
MachXO2 SED Usage Guide
Description
5