Sed Limitations; Sed Operating Modes - Lattice Semiconductor MachXO2 Series Usage Manual

Note that the calculated CRC is based on the particular arrangement of configuration memory for a particular
design. Consequently, the expected CRC results cannot be specified until after the design is placed and routed.
®
The Lattice Diamond
routed design and updates the 32-bit SED CRC register contents during bitstream generation.
The following sections describe the MachXO2 SED implementation and flow.

SED Limitations

SED should only be run when once Vcc reaches the data sheet Vcc minimum recommend level. In addition, clock
frequencies of greater than 33.33 MHz for the SED are not supported.
The clock (SMCLK) of the SED circuit is shared with the Configuration Logic. As a result, the SED module interacts
with several EFB functions with the following results:
• If the EFB or Configuration Logic is accessed while the SED circuit is running:
— The current SED cycle will be terminated:
— When the SED circuit is terminated there will be a delay of two SMCLK cycles before EFB or Config-
uration Logic can be accessed. This is a result of the SMCLK transferring clock from the SED Clock to
the Configuration Clock domain. The two SMCLK cycles are defined by the slower SED clock.
— When the SED circuit is terminated the SEDDONE will remain low, SEDERR will remain low, and
SEDINPROG resets from high to low.
— The EFB or Configuration Logic access which interacts with the SED circuit is defined as:
— The following commands issued through the JTAG port or WISHBONE interface:
— LSC_REFRESH
— ISC_ENABLE
— ISC_ENABLE_X
— All IEEE 1532 instructions
— ISC_DISABLE
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— Primary I
— SPI Configuration Logic chip select being asserted
• The PROGRAMN pin detection logic requires the minimal low period be longer than six SMCLK cycles. If the
SED circuit is running the six SMCLK cycles are defined by the SED clock.

SED Operating Modes

For MachXO2 devices there are two operating modes available for SED:
• Standard mode allows the design to control when the SED is run and to test the error detection operation.
• One-shot operation is used to run the SED once when the device is first configured to ensure that the configura-
tion matches the desired configuration.
Both operations perform a single cycle which checks the CRC of all the bits in the SRAM except the EBR and RAM
memory. Standard mode is activated using the SEDFA primitive while the One-Shot operation is activated using the
SEDFB primitive. These primitives are described in the next section.
If an error is detected during an SED operation, the user can choose one of two corrective actions to take. One is to
"Do Nothing" and the other is to initiate an on-demand user reconfiguration by pulling the PROGRAMN pin low.
This can be done from another device or from an output of the MachXO2 device as shown in Figure 4.
The PROGRAMn pin detection logic requires the minimal low period be longer than 6 SMCLK cycles. When error
detection is actively enabled, the PROGRAMn pin minimal low period will be 6 SEDCLK cycles, since the active
SMCLK switched to SEDCLK as mentioned previously. This will behave differently then normal operation where
the SMCLK is operating at full speed. After booting, the SED function block will behave according to the new con-
figuration programming.
®
or ispLEVER bitstream generation software analyzes the configuration of a placed and
C Configuration Logic slave address match
MachXO2 SED Usage Guide
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