Revision History - Lattice Semiconductor MachXO2 Series Usage Manual

Revision History

Date
January 2017
December 2013
February 2013
January 2013
August 2012
February 2012
July 2011
June 2011
May 2011
January 2011
November 2010
Version
2.0 Updated the
Run Time.
Updated the
Updated document template.
01.9 Updated the body text to match Timing Diagram for SED Operation.
01.8 Removed requirements for holding user logic in a steady state.
01.7 Defined the EFB or Configuration Logic which interacts with the SRAM
CRC Error Detection circuit.
Added timing diagram for SED operation.
Changed "SRAM CRC Error Detection" to "SED" throughout the docu-
ment.
01.6 Updated SRAM CRC Error Detection Limitations and SRAM CRC Error
Detection Operating Modes sections.
01.5 Updated document with new corporate logo.
01.4 Updated Standard SRAM CRC Error Detection text section with infor-
mation about migration from MachXO2-1200-R1 to Standard (N-1)
devices.
01.3 Document title changed from "MachXO2 Soft Error Detection (SED)
Usage Guide" to "MachXO2 SRAM CRC Error Detection Usage Guide".
Clarified attribute usage for SEDFB primitive.
Clarified run time calculation section.
01.2 Changed "SED" to "SRAM CRC Error Detection" throughout the docu-
ment.
Added Limitations section.
Replaced Basic SED Mode and Hardware Description sections with
Operating Modes section and added description of the primitives.
Updated supported frequencies in Table 2, SRAM CRC Error Detection
Internal Oscillator Supported Frequency Settings.
Updated Port descriptions and Flow sections.
Corrected Run Time calculations and updated Table 4, SRAM CRC
Error Detection Run Time.
Updated Sample Code section.
01.1 Updated for ultra-high I/O ("U") devices.
01.0 Initial release.
10
MachXO2 SED Usage Guide
Change Summary
SED Run Time section. Revised values in
Technical Support Assistance
Table 4, SED
section.