System Dac And Acquisition; Control Registers; System Dac (Cont) And Auxiliary Front Panel - Tektronix 2432 Service Manual

Jit 1 Gain and Jit 2 Gain amplifiers and down to about 1
for the CH 1 and CH 2-BAL voltage followers. The Jitter
Gain circuits (formed by U661A and U661 B) produce a
negative 5 V de offset voltage at their output pins as their
gain-setting resistors are referenced to the + 5 V supply.
The DAC Offset and DAC Gain Sample-and-Hold circuit
operations are described in the previous D/A Converter
discussion.
Acquisition Control Registers
Mode control of the analog acquisition system and
trigger circuitry is controlled by the System µP via shift
registers and a decoder. The System µP, through its
address decoding circuitry, enables Decoder U271 to pro-
duce a shift register clock at one of its eight outputs.
These clock signals are used to move serial data from the
ACD (acquisition control data) line, U272 pin 5, into one of
the various Acquisition Control Registers, of which three
are shown in diagram 5. They are Peak Detector Control
Register U530, Gate Array Control Register U270, and
Trigger Source Control Register U140. Other registers
clocked are the Channel 1 and Channel 2 Control Regis-
ters (U510 and U220 on diagram 9), the internal control
registers of the CH 1 and CH 2 Preamplifiers (U420 and
U320 on diagram 9), and the internal control registers in
the A/B Trigger Generator (U 150, diagram 11 ).
The ACD line is shared by all the Acquisition Control
Registers; the selected clock determines which register will
be loaded with the data being written by the System µP.
Decoder U271 is enabled when the ACOSEL and WR lines
are LO and address line A3 is HI. Address lines AO, A1,
A2 determine which of the output lines produces the clock
signal. A data bit present on the ACD line (previously writ-
ten to latch U272 in a DAC write cycle) is loaded into the
clocked register on the rising edge of the WR signal as
U271 becomes unenabled and its selected LO output goes
HI. Each bit to be loaded must be successively written to
U272 then moved into a register by the output clock
from U271.
SYSTEM DAC (cont) AND
AUXILIARY FRONT PANEL
The DAC multiplexing and sample-and-hold circuits
included in diagram 6 operate similarly to those described
in the DAC System (diagram 5) discussion. The analog
voltage output from the DAC I-to-E Converter is routed
through one of the three additional multiplexers (shown in
diagram 6) to several types of hold circuits.
Theory of Operation-2432 Service
DAC Multiplexers
DAC Multiplexers U821, U830, and U831 route the
analog output voltage from DAC I-to-E Converter U661 C
(diagram 5) to the various Sample-and-Hold circuits.
Operation of each multiplexer is identical to that of Multi-
plexer U651, previously described in the System DAC cir-
cuit discussion. Each multiplexer is individually enabled by
a bit from Multiplexer Select Latch U272, and signal rout-
ing through the enabled device is controlled by the three
select bits applied to it from the three most significant bit
outputs of DAC Register U851.
Sample-and-Hold
A separate Sample-and-Hold circuit is associated with
each of the multiplexer outputs. An analog voltage routed
from the DAC I-to-E Converter through the selected multi-
plexer channel charges up the hold capacitor at the input
of an operational amplifier in the selected Sample-and-Hold
circuit. When that multiplexer channel is deselected, the
voltage level is held on the capacitor because of the high-
impedance discharge paths presented by the multiplexer
output and the operational amplifier input. The individual
operational amplifiers are configured as buffers with volt-
age gains varying from -0.47 to +10, depending on the
requirements of the function that is being controlled. The
CH 1 and CH 2 Position Sample-and-Hold circuits also
provide a de offset of their output levels to properly bias
the inputs they drive.
Cal Signal Amplifier
The Cal Signal Amplifier (U610) operates in a manner
similar to the Sample-and-Hold circuits just described. It is
used to supply test signals to the CAL inputs of the CH 1
and CH 2 Peak Detectors (U440 and U340, diagram 10)
for Self Calibration of the acquisition system. The test sig-
nal level, stored on capacitor C733, is applied to the input
of an amplifier internal to U610 which has dual-differential
outputs. The complementary-current outputs for each
channel are approximately 6 mA ± 1 .25 mA.
Z-Axis Control
The Z-Axis Control stage consists of 0810, U811,
U81 QA, U81 OB, five-transistor array U812, and associated
components. Multiplexer U811 selects one of three
intensity-control voltages-normal, intensified, or readout
(output from Sample-and-Hold buffers U820B, U820C, or
U820D) and routes it to a current source composed of
U81 0A, U81 OB, and 0810. The amount of current passed
by 0810 controls the display intensity. The transistors in
array U812 form an automatic gain compensation circuit
for Z-Axis Amplifier U227 (diagram 19).
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