Output Data Timing - Motorola SE4710 Integration Manual

6 - 2 SE4710 Integration Guide

Output Data Timing

Data output is synchronized with the PIXCLK output. When LINE_VALID is high, one 8-bit pixel datum is output
every PIXCLK period.
FRAME_VALID
LINE_VALID
Number of Pixel Clocks
Row Timing and FRAME_VALID / LINE_VALID Signals
Figure 6-2
LINE_VALID
PIX CLK
Blanking
D
OUT (7:0)
Pixel Data Timing Example
Figure 6-3
Frame Time @ 42 MHz
Table 6-1
Parameter
A
P1
P2
Q
A + Q
V
Nrows
F
. . .
. . .
. . .
P1 A Q
Valid Image Data
P 0 P 1
Description
Active data time 1280
With stats enabled 1360
Frame start blanking 18
Frame end blanking 14
Horizontal blanking 408
With stats enabled 328
Row time 1688
Vertical blanking 47,638
With stats enabled 47,558
Frame 1,350,024
With stats enabled 1,350,104
Total 1,397,662
A Q A
. . . .
. . . .
. . . .
P P 3 P 4
. . . .
2
Pixel Clock Time
30.48
32.38
0.43
0.33
9.71
7.81
40.19
1.13
1.13
32.14
32.15
33.28
P2
Blanking
P n-1 P n
Units
µs
µs
µs
µs
µs
µs
µs
ms
ms
ms
ms
ms