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USB Audio Design Guide
The
setting P4E[0] and P4E[1] low. It then selects the required master clock and keeps
both the DAC and ADC in reset for a period in order allow the clocks to stabilize.
The DAC and ADC are brought out of reset by setting P4E[0] and P4E[1] back high.
Various registers are then written to the ADC and DAC as required.
6.5.5 Validated Build Options
The reference design can be built in several ways by changing the build options.
These are described in §7.1.
The design has only been fully validated against the build options as set in the
application as distributed. See
These fully validated build configurations are listed below. In practise, due to the
similarities between the U-Series and L-Series feature set, it is fully expected that
all listed U-Series configurations will operate as expected on the L-Series and vice
versa.
6.5.5.1 Configuration 2ioxs
This configuration runs in high-speed Audio Class 2.0 mode, has the mixer core is
enabled (for volume processing only, supports 10 channels in, 10 channels out,
supports sample rates up to 192kHz and S/PDIF transmit.
6.6 The xCORE-200 Multi-Channel Audio Board
An application of the USB audio framework is provided specifically for the hardware
described in
related code can be found in app_usb_aud_xk_216_mc.
The design supports upto 10 channels of analogue audio input/output at sample-
rates up to 192kHz assuming the use of I2S. This can be further increased by
utilising TDM.
The design uses the following components:
XMOS USB Device Driver (XUD)
Endpoint 0
Endpoint buffer
Decoupler
Audio Driver
Device Firmware Upgrade (DFU)
XM0088546.1
AudioHwConfig()
function first puts the both the DAC and ADC into reset by
§2.1
and is implemented on an xCORE-200-series dual tile device. The
§5.3
for details and binary naming scheme.
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