Dac And Adc Configuration; Audiohwinit(); Audiohwconfig() - XMOS xCORE-200 Multi-channel Audio board Design Manual

USB Audio Design Guide
The master clock source is controlled by a mux which, in turn, is controlled by bit
1 of PORT 4D:
Figure 38:
Value
Master Clock
Source 0
Selection
1
The current version of the supplied application only supports the use of the fixed
master-clocks from the PhaseLink part.
The clock-select from the phaselink part is controlled via bit 2 of PORT 4E:
Figure 39:
Value
Master Clock
Frequency 0
Select
1
6.5.2 DAC and ADC Configuration
The board is equipped with a single multi-channel audio DAC (Cirrus Logic CS4384)
and a single multi-channel ADC (Cirrus Logic CS5368) giving 8 channels of analogue
output and 8 channels of analogue input.
Configuration of both the DAC and ADC takes place using I2C. The design uses
the I2C component sc_i2c
The reset lines of the DAC and ADC are connected to bits 0 and 1 of PORT 4E
respectively.

6.5.3 AudioHwInit()

The
Initialise the I2C master software module
Puts the audio hardware into reset
Enables the power to the audio hardware
Select the PhaseLink PLL as the audio master clock source.
6.5.4 AudioHwConfig()
The
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http://www.github.com/xcore/sc_i2c
XM0088546.1
Source
Master clock is sourced from PhaseLink PLL
Master clock is source from Cirrus Clock Multiplier
Frequency
24.576MHz
22.579MHz
AudioHwInit() function is implemented to perform the following:
AudioHwConfig() function is called on every sample frequency change.
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