Usage And Integration - XMOS xCORE-200 Multi-channel Audio board Design Manual

USB Audio Design Guide
The S/PDIF receiver module uses a clockblock and a buffered one-bit port. The
clock-block is divided of a 100 MHz reference clock. The one bit port is buffered
to 4-bits. The receiver code uses this clock to over sample the input data.
The receiver outputs audio samples over a streaming channel end where data can
be input using the built-in input operator.
The S/PDIF receive function never returns. The 32-bit value from the channel input
comprises:
Bits
Figure 22:
0:3
S/PDIF RX
Word 4:28
Structure
29:31
The tag has one of three values:
Tag
FRAME_X
Figure 23:
FRAME_Y
S/PDIF RX
FRAME_Z
Tags
See S/PDIF specification for further details on format, user bits etc.

3.8.1 Usage and Integration

Since S/PDIF is a digital steam the devices master clock must be syncronised to it.
This is typically done with an external fractional-n multipier. See Clock Recovery
(§3.10)
The S/PDIF receive function communicates with the clockGen component with
passes audio data to the audio driver and handles locking to the S/PDIF clock
source if required (see External Clock Recovery).
Ideally the parity of each word/sample received should be checked. This is done
using the built in crc32 function (see xs1.h ):
/* Returns 1 for bad parity , else 0 */
static inline int badParity ( unsigned x )
{
}
If bad parity is detected the word/sample is ignored, otherwise the tag is inspected
for channel (i.e. left or right) and the sample stored.
XM0088546.1
A tag (see below)
PCM encoded sample value
User bits (parity, etc)
Meaning
Sample on channel 0 (Left for stereo)
Sample on another channel (Right if for stereo)
Sample on channel 0 (Left), and the first sample of a frame; can be used if
the user bits need to be reconstructed.
unsigned X = (x > >4) ;
crc32 (X , 0 , 1) ;
return X & 1;
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