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XC-1 Hardware Manual
Version 1.3.2
Publication Date: 2009/11/12
Copyright
© 2009 XMOS Ltd. All Rights Reserved.
Downloaded from
Elcodis.com
electronic components distributor

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Summary of Contents for XMOS XC-1

  • Page 1 XC-1 Hardware Manual Version 1.3.2 Publication Date: 2009/11/12 Copyright © 2009 XMOS Ltd. All Rights Reserved. Downloaded from Elcodis.com electronic components distributor...
  • Page 2 E Four I/O Expansion Areas J USB 2.0 to JTAG The XC-1 Development Kit also includes a USB cable for powering and booting the device from a PC. The card is fitted with four plastic feet, which are useful for building bigger prototyping systems.
  • Page 3 3/17 2 XS1-G4 Device [A] The XC-1 provides a single four core XS1-G4 device in a 512BGA package. Each XCore is programmable and comprises an event-driven multi-threaded processor with tightly integrated general purpose I/O pins and 64 KBytes of on-chip RAM. The pins on XCore0 and XCore2 are brought out of the package and connected to the card’s components as follows:...
  • Page 4 XC-1 Hardware Manual (1.3.2) 4/17 To reduce the number of pins required for the 12 clock-LEDs, the LED anodes are connected to three 4-bit ports (4A, 4B and 4C) on processor 0 and the cathodes are connected to two 1-bit ports (1E for green, 1F for red) that are active high.
  • Page 5 XC-1 Hardware Manual (1.3.2) 5/17 PORT_CLOCKLED_SELR PORT_CLOCKLED_SELG Colour Off Green To get yellow, alternate green/red in 4:1 ratio The clock LED pins are mapped to ports as described in the table below: Port Processor X0D2 P4A0 PORT_CLOCKLED_0 [IIII] X0D3 P4A1 PORT_CLOCKLED_0 [V]...
  • Page 6 6/17 4 Push-Button Switches [D] The XC-1 provides four push-button switches whose states can be sampled at any time by software. Pushing a button results in a 0 signal, unpushed the signal is 1. The layout of the push-buttons is shown below.
  • Page 7 XC-1 Hardware Manual (1.3.2) 7/17 5 I/O Expansion Areas [E] The I/O pins of processor 2 are brought out to expansion areas on both sides of the card. These areas have 0.1” pitch plated through holes and are suitable for use with IDC headers.
  • Page 8 XC-1 Hardware Manual (1.3.2) 8/17 Port Processor X2D0 P1A0 X2D1 P1B0 X2D2 P4A0 P8A0 P16A0 X2D3 P4A1 P8A1 P16A1 X2D4 P4B0 P8A2 P16A2 X2D5 P4B1 P8A3 P16A3 X2PortA X2D6 P4B2 P8A4 P16A4 X2D7 P4B3 P8A5 P16A5 X2D8 P4A2 P8A6 P16A6...
  • Page 9 XC-1 Hardware Manual (1.3.2) 9/17 5.1 XMOS Link Configuration Some of the I/O pins on the expansion header can be configured as XMOS Links. The mapping of XMOS Links to the headers is shown in the table below. Header 2/A...
  • Page 10 XC-1 Hardware Manual (1.3.2) 10/17 6 Prototyping Area [F] The XC-1 provides a 0.1” pitch plated through hole area for adding components to the card. The routing of I/O and power pins in the prototyping area is shown below. X0D39...
  • Page 11 XC-1 Hardware Manual (1.3.2) 11/17 Port Processor X0D0 P1A0 X0D1 P1B0 X0D10 P1C0 X0D11 P1D0 X0D26 P4E0 P8C0 X0D27 P4E1 P8C1 X0D28 P4F0 P8C2 X0D29 P4F1 P8C3 Prototyping Area X0D30 P4F2 P8C4 X0D31 P4F3 P8C5 X0D32 P4E2 P8C6 X0D33 P4E3 P8C7...
  • Page 12 12/17 7 Speaker [G] The XC-1 has a speaker. The layout of the speaker is shown below. Audio signals are generated by filtering pulse width modulated (PWM) digital signals to form an analogue waveform, which is amplified and sent to the speaker, as shown...
  • Page 13 XC-1 Hardware Manual (1.3.2) 13/17 8 USB Connector [H and J] The XC-1 is powered directly from a host PC using a USB connector. The 5V voltage is converted by the on-board regulator to the 1V and 3V3 supplies used by the components.
  • Page 14 XC-1 Hardware Manual (1.3.2) 14/17 10 Dimensions The XC-1 dimensions are 86 x 54mm. The mounting holes are 3mm in diameter. 11 XC-1 Block Diagram The diagram below shows how the XC-1 components are connected to the XS1-G4. Processor 0...
  • Page 15 XC-1 Hardware Manual (1.3.2) 15/17 11.1 I/O Port-to-Pin Mapping The table below provides a full description of the port-to-pin mappings described throughout this document. Port Processor XnD0 P1A0 PROTOTYPE_AREA_0 XnD1 P1B0 PROTOTYPE_AREA_1 XnD2 P4A0 P8A0 P16A0 PORT_CLOCKLED_0 [IIII] XnD3 P4A1 P8A1 P16A1...
  • Page 16 16/17 12 XC-1 XN File The XCore ports linked to the hardware features on the XC-1 are mapped to generic port identifiers as part of a platform specific XN file, which simplifies the process of porting a project between platforms.
  • Page 17 “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims.